RUBATTU, CLAUDIO
RUBATTU, CLAUDIO
DIPARTIMENTO DI INGEGNERIA ELETTRICA ED ELETTRONICA
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Feasibility study and porting of the damped least square algorithm on FPGA
2020-01-01 Sau, C.; Fanni, T.; Rubattu, C.; Fanni, L.; Raffo, L.; Palumbo, F.
The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design
2020-01-01 Sau, C.; Fanni, T.; Rubattu, C.; Raffo, L.; Palumbo, F.
Dataflow-functional high-level synthesis for coarse-grained reconfigurable accelerators
2019-01-01 Rubattu, Claudio; Palumbo, Francesca; Sau, Carlo; Salvador, Ruben; Serot, Jocelyn; Desnos, Karol; Raffo, Luigi; Pelcat, Maxime
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs
2017-01-01 Meloni, P.; Rubattu, C.; Tuveri, G.; Pani, D.; Raffo, L.; Palumbo, F.
| Titolo | Data di pubblicazione | Autore(i) | Rivista | Editore |
|---|---|---|---|---|
| Feasibility study and porting of the damped least square algorithm on FPGA | 1-gen-2020 | Sau, C.; Fanni, T.; Rubattu, C.; Fanni, L.; Raffo, L.; Palumbo, F. | IEEE ACCESS | - |
| The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design | 1-gen-2020 | Sau, C.; Fanni, T.; Rubattu, C.; Raffo, L.; Palumbo, F. | MICROPROCESSORS AND MICROSYSTEMS | - |
| Dataflow-functional high-level synthesis for coarse-grained reconfigurable accelerators | 1-gen-2019 | Rubattu, Claudio; Palumbo, Francesca; Sau, Carlo; Salvador, Ruben; Serot, Jocelyn; Desnos, Karol; Raffo, Luigi; Pelcat, Maxime | IEEE EMBEDDED SYSTEMS LETTERS | - |
| Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs | 1-gen-2017 | Meloni, P.; Rubattu, C.; Tuveri, G.; Pani, D.; Raffo, L.; Palumbo, F. | JOURNAL OF SYSTEMS ARCHITECTURE | - |