<?xml version="1.0" encoding="UTF-8"?><?xml-stylesheet type="text/xsl" href="static/CINECAstyle.xsl"?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-09-19T19:58:10Z</responseDate><request verb="GetRecord" identifier="oai:iris.unica.it:11584/266751" metadataPrefix="oai_dc">https://iris.unica.it/oai/request</request><GetRecord><record><header><identifier>oai:iris.unica.it:11584/266751</identifier><datestamp>2022-10-20T10:07:10Z</datestamp><setSpec>com_11584_207615</setSpec><setSpec>com_11584_111066</setSpec><setSpec>col_11584_265854</setSpec></header><metadata><oai_dc:dc xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/" xmlns:doc="http://www.lyncode.com/xoai" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:dc="http://purl.org/dc/elements/1.1/" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/oai_dc/ http://www.openarchives.org/OAI/2.0/oai_dc.xsd">
<dc:title>Dataflow based design suite for the development and management of multi-functional reconfigurable systems</dc:title>
<dc:creator>SAU, CARLO</dc:creator>
<dc:subject>accelleratori hardware</dc:subject>
<dc:subject>coarse grained reconfigurability</dc:subject>
<dc:subject>controllo del consumo di potenza</dc:subject>
<dc:subject>dataflow model of computation</dc:subject>
<dc:subject>hardware accelerators</dc:subject>
<dc:subject>modello di computazione dataflow</dc:subject>
<dc:subject>paradigma riconfigurabile</dc:subject>
<dc:subject>power management</dc:subject>
<dc:subject>reconfigurable computing</dc:subject>
<dc:subject>riconfigurabilità a grana grossa</dc:subject>
<dc:subject>Settore ING-INF/01 - Elettronica</dc:subject>
<dc:description>Embedded systems development constitutes an extremely challenging scenario for the designers since several constraints have to be meet at the same time. Flexibil- ity, performance and power efficiency are typically colliding requirements that are hardly addressed together. Reconfigurable systems provide a valuable alternative to common architectures to challenge contemporarily all those issues. Such a kind of systems, and in particular the coarse grained ones, exhibit a certain level of flexi- bility while guaranteeing strong performance. However they suffer of an increased design and management complexity. In this thesis it is discussed a fully automated methodology for the development of coarse grained reconfigurable platforms, by exploiting dataflow models for the de- scription of the desired functionalities. The thesis describes, actually, a whole design suite that offers, besides the reconfigurable substrate composition, also structural optimisation, dynamic power management and co-processing support. All the pro- vided features have been validated on different signal, image and video processing scenarios, targeting either FPGA and ASIC.</dc:description>
<dc:date>2016-03-30</dc:date>
<dc:type>info:eu-repo/semantics/doctoralThesis</dc:type>
<dc:identifier>http://hdl.handle.net/11584/266751</dc:identifier>
<dc:language>eng</dc:language>
<dc:relation>numberofpages:159</dc:relation>
<dc:rights>info:eu-repo/semantics/openAccess</dc:rights>
<dc:publisher>Università degli Studi di Cagliari</dc:publisher>
<dc:rights>license:Non specificato</dc:rights>
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