Impact of threshold computation methods in hardware wavelet denoising implementations for neural signal processing

Wavelet denoising effectiveness has been proven in neural signal processing applications characterized by a low SNR. This nonlinear approach is implemented through the application of some thresholds on the detail signals coming from a sub-band decomposition. The computation of the thresholds could exhibit a high latency when involving some estimators such as the Median Absolute Deviation (MAD), which is critical for real-time applications. When a VLSI implementation is pursued for low-power purposes, such as in the neuroprosthetic field, these aspects cannot be overlooked. This paper presents an analysis of the main VLSI hardware implementation figures related to this specific aspect of the signal denoising by wavelet processing. Xilinx System Generator has been exploited as a design and co-simulation tool to ease the hardware development on off-the-shelf FPGA platforms. The MAD estimator has been both combinatorially and sequentially implemented, and compared against the sample standard deviation. The study reveals similar performance on the neural signals but dramatically worse implementation figures for the MAD. The combinatorial version of the MAD actually prevents an efficient implementation on medium-small devices. This result is important to perform a correct implementation choice for implantable real-time systems, where the device size is relevant for an usable realization.