SAU, CARLO
SAU, CARLO
A coarse-grained reconfigurable wavelet denoiser exploiting the multi-dataflow composer tool
2013-01-01 Carta, N; Sau, Carlo; Palumbo, Francesca; Pani, Danilo; Raffo, Luigi
Adaptable AES implementation with power-gating support
2016-01-01 Banik, Subhadeep; Bogdanov, Andrey; Fanni, Tiziana; Sau, Carlo; Raffo, Luigi; Palumbo, Francesca; Regazzoni, Francesco
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case
2014-01-01 Sau, Carlo; Raffo, Luigi; Palumbo, Francesca; Bezati, E; Casale Brunet, S; Mattavelli, M.
Automated Design Flow for Multi-Functional Dataflow-Based Platforms
2016-01-01 Sau, Carlo; Meloni, Paolo; Raffo, Luigi; Palumbo, Francesca; Bezati, E; Casale Brunet, S; Mattavelli, M.
Automated power gating methodology for dataflow-based reconfigurable systems
2015-01-01 Fanni, Tiziana; Sau, Carlo; Raffo, Luigi; Palumbo, Francesca
Automatic Generation of Dataflow-Based Reconfigurable Co-processing Units
2014-01-01 Sau, Carlo; Palumbo, Francesca
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing
2017-01-01 Sau, Carlo; Palumbo, Francesca; Pelcat, M; Heulot, J; Nogues, E; Menard, D; Meloni, Paolo; Raffo, Luigi
A coarse-grained reconfigurable approach for low-power spike sorting architectures
2013-01-01 Carta, N; Sau, Carlo; Pani, Danilo; Palumbo, Francesca; Raffo, Luigi
Coarse-grained reconfiguration: dataflow-based power management
2015-01-01 Palumbo, Francesca; Sau, Carlo; Raffo, Luigi
Computing swarms for self-adaptiveness and self-organizationin floating-point array processing
2015-01-01 Pani, Danilo; Sau, Carlo; Palumbo, F; Raffo, Luigi
Dataflow based design suite for the development and management of multi-functional reconfigurable systems
2016-03-30
DSE and profiling of multi-context coarse-grained reconfigurable systems
2013-01-01 Palumbo, Francesca; Sau, Carlo; Raffo, Luigi
Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design
2016-01-01 Sau, Carlo; Carta, N; Raffo, Luigi; Palumbo, Francesca
Feasibility study and porting of the damped least square algorithm on FPGA
2020-01-01 Sau, C.; Fanni, T.; Rubattu, C.; Fanni, L.; Raffo, L.; Palumbo, F.
Hardware design methodology using lightweight dataflow and its integration with low power techniques
2017-01-01 Fanni, Tiziana; Li, L; Viitanen, T; Sau, Carlo; Xie, R; Palumbo, F; Raffo, L; Huttunen, H; Takala, J; Bhattacharyya, Ss
An integrated hardware/software design methodology for signal processing systems
2019-01-01 Li, L.; Sau, C.; Fanni, T.; Li, J.; Viitanen, T.; Christophe, F.; Palumbo, F.; Raffo, L.; Huttunen, H.; Takala, J.; Bhattacharyya, S. S.
Modelling and automated implementation of optimal power saving strategies in coarse-grained reconfigurable architectures
2016-01-01 Palumbo, Francesca; Fanni, Tiziana; Sau, Carlo; Meloni, Paolo; Raffo, Luigi
A nature-inspired adaptive floating-point coprocessing system
2012-01-01 Sau, Carlo; Pani, Danilo; Palumbo, Francesca; Raffo, Luigi
Power and clock gating modelling in coarse grained reconfigurable systems
2016-01-01 Fanni, Tiziana; Sau, Carlo; Meloni, Paolo; Raffo, Luigi; Palumbo, Francesca
Power modelling for saving strategies in coarse grained reconfigurable systems
2015-01-01 Fanni, Tiziana; Sau, Carlo; Meloni, Paolo; Raffo, Luigi; Palumbo, Francesca