SAU, CARLO

SAU, CARLO  

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Risultati 1 - 20 di 40 (tempo di esecuzione: 0.066 secondi).
Titolo Data di pubblicazione Autore(i) Rivista Editore
An Automated Design Flow for Adaptive Neural Network Hardware Accelerators 1-gen-2023 Ratto, F.; Mainez, A. P.; Sau, C.; Meloni, P.; Deriu, G.; Delucchi, S.; Massa, M.; Raffo, L.; Palumbo, F. JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL, IMAGE, AND VIDEO TECHNOLOGY -
Multithread Accelerators on FPGAs: A Dataflow-Based Approach 1-gen-2022 Ratto, F.; Esposito, S.; Sau, C.; Raffo, L.; Palumbo, F. - -
A Composable Monitoring System for Heterogeneous Embedded Platforms 1-gen-2021 Valente, G.; Fanni, T.; Sau, C.; Mascio, T. D.; Pomante, L.; Palumbo, F. ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS -
Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project 1-gen-2021 Sau, C.; Rinaldi, C.; Pomante, L.; Palumbo, F.; Valente, G.; Fanni, T.; Martinez, M.; van der Linden, F.; Basten, T.; Geilen, M.; Peeren, G.; Kadlec, J.; Jaaskelainen, P.; Bulej, L.; Barranco, F.; Saarinen, J.; Santti, T.; Zedda, M. K.; Sanchez, V.; Nikkhah, S. T.; Goswami, D.; Amat, G.; Marsik, L.; van Helvoort, M.; Medina, L.; Al-Ars, Z.; de Beer, A. MICROPROCESSORS AND MICROSYSTEMS -
Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators 1-gen-2021 Ratto, Francesco; Fanni, Tiziana; Raffo, Luigi; Sau, Carlo ELECTRONICS -
Runtime adaptive iomt node on multi-core processor platform 1-gen-2021 Scrugli, M. A.; Meloni, P.; Sau, C.; Raffo, L. ELECTRONICS -
Feasibility study and porting of the damped least square algorithm on FPGA 1-gen-2020 Sau, C.; Fanni, T.; Rubattu, C.; Fanni, L.; Raffo, L.; Palumbo, F. IEEE ACCESS -
Layering the monitoring action for improved flexibility and overhead control: Work-in-progress 1-gen-2020 Valente, G.; Fanni, T.; Sau, C.; Di Battista, F. - Institute of Electrical and Electronics Engineers Inc.
NeuPow: A CAD Methodology for High-level Power Estimation Based on Machine Learning 1-gen-2020 Nasser, Y.; Sau, C.; Prevotet, J. -C.; Fanni, T.; Palumbo, F.; Helard, M.; Raffo, L. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS -
The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design 1-gen-2020 Sau, C.; Fanni, T.; Rubattu, C.; Raffo, L.; Palumbo, F. MICROPROCESSORS AND MICROSYSTEMS -
An integrated hardware/software design methodology for signal processing systems 1-gen-2019 Li, L.; Sau, C.; Fanni, T.; Li, J.; Viitanen, T.; Christophe, F.; Palumbo, F.; Raffo, L.; Huttunen, H.; Takala, J.; Bhattacharyya, S. S. JOURNAL OF SYSTEMS ARCHITECTURE -
Dataflow-functional high-level synthesis for coarse-grained reconfigurable accelerators 1-gen-2019 Rubattu, Claudio; Palumbo, Francesca; Sau, Carlo; Salvador, Ruben; Serot, Jocelyn; Desnos, Karol; Raffo, Luigi; Pelcat, Maxime IEEE EMBEDDED SYSTEMS LETTERS -
Multi-grain reconfiguration for advanced adaptivity in cyber-physical systems 1-gen-2019 Fanni, T.; Rodriguez, A.; Sau, C.; Suriano, L.; Palumbo, F.; Raffo, L.; Torre, E. D. L. - Institute of Electrical and Electronics Engineers Inc.
Neu Pow: Artificial Neural Networks for Power and Behavioral Modeling of Arithmetic Components in 45nm ASICs Technology 1-gen-2019 Nasser, Y.; Sau, C.; Prevotet, J. -C.; Fanni, T.; Palumbo, F.; Helard, M.; Raffo, L. - Association for Computing Machinery, Inc
Reconfigurable Adaptive Multiple Transform Hardware Solutions for Versatile Video Coding 1-gen-2019 Sau, C.; Ligas, D.; Fanni, T.; Raffo, L.; Palumbo, F. IEEE ACCESS -
Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems 1-gen-2018 Fanni, T; Rodriguez, A; Sau, C; Suriano, L; Palumbo, F; Raffo, L; de la Torre, E - IEEE
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing 1-gen-2017 Sau, Carlo; Palumbo, Francesca; Pelcat, M; Heulot, J; Nogues, E; Menard, D; Meloni, Paolo; Raffo, Luigi IEEE EMBEDDED SYSTEMS LETTERS -
Hardware design methodology using lightweight dataflow and its integration with low power techniques 1-gen-2017 Fanni, Tiziana; Li, L; Viitanen, T; Sau, Carlo; Xie, R; Palumbo, F; Raffo, L; Huttunen, H; Takala, J; Bhattacharyya, Ss JOURNAL OF SYSTEMS ARCHITECTURE -
Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy 1-gen-2017 Palumbo, Francesca; Fanni, Tiziana; Sau, Carlo; Meloni, Paolo JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL, IMAGE, AND VIDEO TECHNOLOGY -
Adaptable AES implementation with power-gating support 1-gen-2016 Banik, Subhadeep; Bogdanov, Andrey; Fanni, Tiziana; Sau, Carlo; Raffo, Luigi; Palumbo, Francesca; Regazzoni, Francesco - Association for Computing Machinery, Inc