SAU, CARLO
SAU, CARLO
An Automated Design Flow for Adaptive Neural Network Hardware Accelerators
2023-01-01 Ratto, F.; Mainez, A. P.; Sau, C.; Meloni, P.; Deriu, G.; Delucchi, S.; Massa, M.; Raffo, L.; Palumbo, F.
Multithread Accelerators on FPGAs: A Dataflow-Based Approach
2022-01-01 Ratto, F.; Esposito, S.; Sau, C.; Raffo, L.; Palumbo, F.
A Composable Monitoring System for Heterogeneous Embedded Platforms
2021-01-01 Valente, G.; Fanni, T.; Sau, C.; Mascio, T. D.; Pomante, L.; Palumbo, F.
Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project
2021-01-01 Sau, C.; Rinaldi, C.; Pomante, L.; Palumbo, F.; Valente, G.; Fanni, T.; Martinez, M.; van der Linden, F.; Basten, T.; Geilen, M.; Peeren, G.; Kadlec, J.; Jaaskelainen, P.; Bulej, L.; Barranco, F.; Saarinen, J.; Santti, T.; Zedda, M. K.; Sanchez, V.; Nikkhah, S. T.; Goswami, D.; Amat, G.; Marsik, L.; van Helvoort, M.; Medina, L.; Al-Ars, Z.; de Beer, A.
Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators
2021-01-01 Ratto, Francesco; Fanni, Tiziana; Raffo, Luigi; Sau, Carlo
Runtime adaptive iomt node on multi-core processor platform
2021-01-01 Scrugli, M. A.; Meloni, P.; Sau, C.; Raffo, L.
The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design
2021-01-01 Sau, C.; Fanni, T.; Rubattu, C.; Raffo, L.; Palumbo, F.
Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project
2020-01-01 Pomante, Luigi; Palumbo, Francesca; Rinaldi, Claudia; Valente, Giacomo; Sau, Carlo; Fanni, Tiziana; Linden, Frank van der; Basten, Twan; Geilen, Marc; Peeren, Geran; Kadlec, Jiri; Jaaskelainen, Pekka; Martinez, Marcos; Saarinen, Jukka; Santti, Tero; Zedda, Maria Katiuscia; Sanchez, Victor; Goswami, Dip; Al-Ars, Zaid; Beer, Ad de
Feasibility study and porting of the damped least square algorithm on FPGA
2020-01-01 Sau, C.; Fanni, T.; Rubattu, C.; Fanni, L.; Raffo, L.; Palumbo, F.
Layering the monitoring action for improved flexibility and overhead control: Work-in-progress
2020-01-01 Valente, G.; Fanni, T.; Sau, C.; Di Battista, F.
NeuPow: A CAD Methodology for High-level Power Estimation Based on Machine Learning
2020-01-01 Nasser, Y.; Sau, C.; Prevotet, J. -C.; Fanni, T.; Palumbo, F.; Helard, M.; Raffo, L.
An integrated hardware/software design methodology for signal processing systems
2019-01-01 Li, L.; Sau, C.; Fanni, T.; Li, J.; Viitanen, T.; Christophe, F.; Palumbo, F.; Raffo, L.; Huttunen, H.; Takala, J.; Bhattacharyya, S. S.
Dataflow-functional high-level synthesis for coarse-grained reconfigurable accelerators
2019-01-01 Rubattu, Claudio; Palumbo, Francesca; Sau, Carlo; Salvador, Ruben; Serot, Jocelyn; Desnos, Karol; Raffo, Luigi; Pelcat, Maxime
Neu Pow: Artificial Neural Networks for Power and Behavioral Modeling of Arithmetic Components in 45nm ASICs Technology
2019-01-01 Nasser, Y.; Sau, C.; Prevotet, J. -C.; Fanni, T.; Palumbo, F.; Helard, M.; Raffo, L.
Reconfigurable Adaptive Multiple Transform Hardware Solutions for Versatile Video Coding
2019-01-01 Sau, C.; Ligas, D.; Fanni, T.; Raffo, L.; Palumbo, F.
Reconfigurable and approximate computing for video coding
2019-01-01 Palumbo, Francesca; Sau, Carlo
Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAPI
2019-01-01 Fanni, Tiziana; Madroñal, Daniel; Rubattu, Claudio; Sau, Carlo; Palumbo, Francesca; Juárez, Eduardo; Pelcat, Maxime; Sanz, Cesar; Raffo, Luigi
Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems
2018-01-01 Fanni, T; Rodriguez, A; Sau, C; Suriano, L; Palumbo, F; Raffo, L; de la Torre, E
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing
2017-01-01 Sau, Carlo; Palumbo, Francesca; Pelcat, M; Heulot, J; Nogues, E; Menard, D; Meloni, Paolo; Raffo, Luigi
Hardware design methodology using lightweight dataflow and its integration with low power techniques
2017-01-01 Fanni, Tiziana; Li, L; Viitanen, T; Sau, Carlo; Xie, R; Palumbo, F; Raffo, L; Huttunen, H; Takala, J; Bhattacharyya, Ss
| Titolo | Data di pubblicazione | Autore(i) | Rivista | Editore |
|---|---|---|---|---|
| An Automated Design Flow for Adaptive Neural Network Hardware Accelerators | 1-gen-2023 | Ratto, F.; Mainez, A. P.; Sau, C.; Meloni, P.; Deriu, G.; Delucchi, S.; Massa, M.; Raffo, L.; Palumbo, F. | JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL, IMAGE, AND VIDEO TECHNOLOGY | - |
| Multithread Accelerators on FPGAs: A Dataflow-Based Approach | 1-gen-2022 | Ratto, F.; Esposito, S.; Sau, C.; Raffo, L.; Palumbo, F. | - | - |
| A Composable Monitoring System for Heterogeneous Embedded Platforms | 1-gen-2021 | Valente, G.; Fanni, T.; Sau, C.; Mascio, T. D.; Pomante, L.; Palumbo, F. | ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS | - |
| Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project | 1-gen-2021 | Sau, C.; Rinaldi, C.; Pomante, L.; Palumbo, F.; Valente, G.; Fanni, T.; Martinez, M.; van der Linden, F.; Basten, T.; Geilen, M.; Peeren, G.; Kadlec, J.; Jaaskelainen, P.; Bulej, L.; Barranco, F.; Saarinen, J.; Santti, T.; Zedda, M. K.; Sanchez, V.; Nikkhah, S. T.; Goswami, D.; Amat, G.; Marsik, L.; van Helvoort, M.; Medina, L.; Al-Ars, Z.; de Beer, A. | MICROPROCESSORS AND MICROSYSTEMS | - |
| Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators | 1-gen-2021 | Ratto, Francesco; Fanni, Tiziana; Raffo, Luigi; Sau, Carlo | ELECTRONICS | - |
| Runtime adaptive iomt node on multi-core processor platform | 1-gen-2021 | Scrugli, M. A.; Meloni, P.; Sau, C.; Raffo, L. | ELECTRONICS | - |
| The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design | 1-gen-2021 | Sau, C.; Fanni, T.; Rubattu, C.; Raffo, L.; Palumbo, F. | MICROPROCESSORS AND MICROSYSTEMS | - |
| Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project | 1-gen-2020 | Pomante, Luigi; Palumbo, Francesca; Rinaldi, Claudia; Valente, Giacomo; Sau, Carlo; Fanni, Tiziana; Linden, Frank van der; Basten, Twan; Geilen, Marc; Peeren, Geran; Kadlec, Jiri; Jaaskelainen, Pekka; Martinez, Marcos; Saarinen, Jukka; Santti, Tero; Zedda, Maria Katiuscia; Sanchez, Victor; Goswami, Dip; Al-Ars, Zaid; Beer, Ad de | - | IEEE |
| Feasibility study and porting of the damped least square algorithm on FPGA | 1-gen-2020 | Sau, C.; Fanni, T.; Rubattu, C.; Fanni, L.; Raffo, L.; Palumbo, F. | IEEE ACCESS | - |
| Layering the monitoring action for improved flexibility and overhead control: Work-in-progress | 1-gen-2020 | Valente, G.; Fanni, T.; Sau, C.; Di Battista, F. | - | Institute of Electrical and Electronics Engineers Inc. |
| NeuPow: A CAD Methodology for High-level Power Estimation Based on Machine Learning | 1-gen-2020 | Nasser, Y.; Sau, C.; Prevotet, J. -C.; Fanni, T.; Palumbo, F.; Helard, M.; Raffo, L. | ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS | - |
| An integrated hardware/software design methodology for signal processing systems | 1-gen-2019 | Li, L.; Sau, C.; Fanni, T.; Li, J.; Viitanen, T.; Christophe, F.; Palumbo, F.; Raffo, L.; Huttunen, H.; Takala, J.; Bhattacharyya, S. S. | JOURNAL OF SYSTEMS ARCHITECTURE | - |
| Dataflow-functional high-level synthesis for coarse-grained reconfigurable accelerators | 1-gen-2019 | Rubattu, Claudio; Palumbo, Francesca; Sau, Carlo; Salvador, Ruben; Serot, Jocelyn; Desnos, Karol; Raffo, Luigi; Pelcat, Maxime | IEEE EMBEDDED SYSTEMS LETTERS | - |
| Neu Pow: Artificial Neural Networks for Power and Behavioral Modeling of Arithmetic Components in 45nm ASICs Technology | 1-gen-2019 | Nasser, Y.; Sau, C.; Prevotet, J. -C.; Fanni, T.; Palumbo, F.; Helard, M.; Raffo, L. | - | Association for Computing Machinery, Inc |
| Reconfigurable Adaptive Multiple Transform Hardware Solutions for Versatile Video Coding | 1-gen-2019 | Sau, C.; Ligas, D.; Fanni, T.; Raffo, L.; Palumbo, F. | IEEE ACCESS | - |
| Reconfigurable and approximate computing for video coding | 1-gen-2019 | Palumbo, Francesca; Sau, Carlo | - | IET |
| Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAPI | 1-gen-2019 | Fanni, Tiziana; Madroñal, Daniel; Rubattu, Claudio; Sau, Carlo; Palumbo, Francesca; Juárez, Eduardo; Pelcat, Maxime; Sanz, Cesar; Raffo, Luigi | - | - |
| Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems | 1-gen-2018 | Fanni, T; Rodriguez, A; Sau, C; Suriano, L; Palumbo, F; Raffo, L; de la Torre, E | - | IEEE |
| Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing | 1-gen-2017 | Sau, Carlo; Palumbo, Francesca; Pelcat, M; Heulot, J; Nogues, E; Menard, D; Meloni, Paolo; Raffo, Luigi | IEEE EMBEDDED SYSTEMS LETTERS | - |
| Hardware design methodology using lightweight dataflow and its integration with low power techniques | 1-gen-2017 | Fanni, Tiziana; Li, L; Viitanen, T; Sau, Carlo; Xie, R; Palumbo, F; Raffo, L; Huttunen, H; Takala, J; Bhattacharyya, Ss | JOURNAL OF SYSTEMS ARCHITECTURE | - |