Adaptable AES implementation with power-gating support

In this paper, we propose a reconfigurable design of the Ad-vanced Encryption Standard capable of adapting at run-Time to the requirements of the target application. Reconfiguration is achieved by activating only a specific subset of all the instantiated processing elements. Further, we explore the effectiveness of power gating and clock gating methodologies to minimize the energy consumption of the processing elements not involved in computation.