PALUMBO, FRANCESCA
PALUMBO, FRANCESCA
A coarse-grained reconfigurable wavelet denoiser exploiting the multi-dataflow composer tool
2013-01-01 Carta, N; Sau, Carlo; Palumbo, Francesca; Pani, Danilo; Raffo, Luigi
Adaptable AES implementation with power-gating support
2016-01-01 Banik, Subhadeep; Bogdanov, Andrey; Fanni, Tiziana; Sau, Carlo; Raffo, Luigi; Palumbo, Francesca; Regazzoni, Francesco
ALOHA: An architectural-aware framework for deep learning at the edge
2018-01-01 Meloni, P.; Loi, D.; Deriu, G.; Ripolles, O.; Solans, D.; Pimentel, A. D.; Sapra, D.; Pintor, Maura; Biggio, B.; Moser, B.; Shepeleva, N.; Stefanov, T.; Minakova, S.; Conti, F.; Benini, L.; Fragoulis, N.; Theodorakopoulos, I.; Masin, M.; Palumbo, F.
Architecture-aware design and implementation of CNN algorithms for embedded inference: The ALOHA project
2018-01-01 Meloni, P.; Loi, D.; Deriu, G.; Pimentel, A. D.; Saprat, D.; Pintor, M.; Biggio, B.; Ripolles, O.; Solans, D.; Conti, F.; Benini, L.; Stefanov, T.; Minakova, S.; Moser, B.; Shepeleva, N.; Masin, M.; Palumbo, F.; Fragoulis, N.; Theodorakopoulos, I.
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case
2014-01-01 Sau, Carlo; Raffo, Luigi; Palumbo, Francesca; Bezati, E; Casale Brunet, S; Mattavelli, M.
Automated Design Flow for Multi-Functional Dataflow-Based Platforms
2016-01-01 Sau, Carlo; Meloni, Paolo; Raffo, Luigi; Palumbo, Francesca; Bezati, E; Casale Brunet, S; Mattavelli, M.
Automated power gating methodology for dataflow-based reconfigurable systems
2015-01-01 Fanni, Tiziana; Sau, Carlo; Raffo, Luigi; Palumbo, Francesca
Automatic Generation of Dataflow-Based Reconfigurable Co-processing Units
2014-01-01 Sau, Carlo; Palumbo, Francesca
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing
2017-01-01 Sau, Carlo; Palumbo, Francesca; Pelcat, M; Heulot, J; Nogues, E; Menard, D; Meloni, Paolo; Raffo, Luigi
A coarse-grained reconfigurable approach for low-power spike sorting architectures
2013-01-01 Carta, N; Sau, Carlo; Pani, Danilo; Palumbo, Francesca; Raffo, Luigi
Coarse-Grained Reconfigurable Approach for Multi-Dataflow Systems
2011-01-01 Carta, N; Palumbo, Francesca; Raffo, Luigi
Coarse-grained reconfiguration: dataflow-based power management
2015-01-01 Palumbo, Francesca; Sau, Carlo; Raffo, Luigi
Concurrent hybrid switching for massively parallel systems-on-chip: The CYBER architecture
2012-01-01 Palumbo, Francesca; Pani, Danilo; Congiu, Andrea; Raffo, Luigi
Design IP Faster: Introducing the C~ High-Level Language
2012-01-01 Wipliez, M; Siret, N; Carta, N; Palumbo, Francesca; Raffo, Luigi
DSE and profiling of multi-context coarse-grained reconfigurable systems
2013-01-01 Palumbo, Francesca; Sau, Carlo; Raffo, Luigi
Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design
2016-01-01 Sau, Carlo; Carta, N; Raffo, Luigi; Palumbo, Francesca
Exploring custom heterogeneous MPSoCs for real-time neural signal decoding
2015-01-01 Meloni, Paolo; Tuveri, Giuseppe; Pani, Danilo; Raffo, Luigi; Palumbo, Francesca
A fast MPI-based parallel framework for cycle-accurate HDL multi-parametric simulations
2010-01-01 Pani, Danilo; Palumbo, Francesca; Raffo, Luigi
Feasibility study and porting of the damped least square algorithm on FPGA
2020-01-01 Sau, C.; Fanni, T.; Rubattu, C.; Fanni, L.; Raffo, L.; Palumbo, F.
An FPGA platform for real-time simulation of spiking neuronal networks
2017-01-01 Pani, Danilo; Meloni, Paolo; Tuveri, Giuseppe; Palumbo, Francesca; Massobrio, Paolo; Raffo, Luigi
| Titolo | Data di pubblicazione | Autore(i) | Rivista | Editore |
|---|---|---|---|---|
| A coarse-grained reconfigurable wavelet denoiser exploiting the multi-dataflow composer tool | 1-gen-2013 | Carta, N; Sau, Carlo; Palumbo, Francesca; Pani, Danilo; Raffo, Luigi | - | IEEE |
| Adaptable AES implementation with power-gating support | 1-gen-2016 | Banik, Subhadeep; Bogdanov, Andrey; Fanni, Tiziana; Sau, Carlo; Raffo, Luigi; Palumbo, Francesca; Regazzoni, Francesco | - | Association for Computing Machinery, Inc |
| ALOHA: An architectural-aware framework for deep learning at the edge | 1-gen-2018 | Meloni, P.; Loi, D.; Deriu, G.; Ripolles, O.; Solans, D.; Pimentel, A. D.; Sapra, D.; Pintor, Maura; Biggio, B.; Moser, B.; Shepeleva, N.; Stefanov, T.; Minakova, S.; Conti, F.; Benini, L.; Fragoulis, N.; Theodorakopoulos, I.; Masin, M.; Palumbo, F. | - | Association for Computing Machinery |
| Architecture-aware design and implementation of CNN algorithms for embedded inference: The ALOHA project | 1-gen-2018 | Meloni, P.; Loi, D.; Deriu, G.; Pimentel, A. D.; Saprat, D.; Pintor, M.; Biggio, B.; Ripolles, O.; Solans, D.; Conti, F.; Benini, L.; Stefanov, T.; Minakova, S.; Moser, B.; Shepeleva, N.; Masin, M.; Palumbo, F.; Fragoulis, N.; Theodorakopoulos, I. | - | Institute of Electrical and Electronics Engineers Inc. |
| Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case | 1-gen-2014 | Sau, Carlo; Raffo, Luigi; Palumbo, Francesca; Bezati, E; Casale Brunet, S; Mattavelli, M. | - | IEEE |
| Automated Design Flow for Multi-Functional Dataflow-Based Platforms | 1-gen-2016 | Sau, Carlo; Meloni, Paolo; Raffo, Luigi; Palumbo, Francesca; Bezati, E; Casale Brunet, S; Mattavelli, M. | JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL, IMAGE, AND VIDEO TECHNOLOGY | - |
| Automated power gating methodology for dataflow-based reconfigurable systems | 1-gen-2015 | Fanni, Tiziana; Sau, Carlo; Raffo, Luigi; Palumbo, Francesca | - | Association for Computing Machinery |
| Automatic Generation of Dataflow-Based Reconfigurable Co-processing Units | 1-gen-2014 | Sau, Carlo; Palumbo, Francesca | - | IEEE |
| Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing | 1-gen-2017 | Sau, Carlo; Palumbo, Francesca; Pelcat, M; Heulot, J; Nogues, E; Menard, D; Meloni, Paolo; Raffo, Luigi | IEEE EMBEDDED SYSTEMS LETTERS | - |
| A coarse-grained reconfigurable approach for low-power spike sorting architectures | 1-gen-2013 | Carta, N; Sau, Carlo; Pani, Danilo; Palumbo, Francesca; Raffo, Luigi | - | Institute of Electrical and Electronics Engineers (IEEE) |
| Coarse-Grained Reconfigurable Approach for Multi-Dataflow Systems | 1-gen-2011 | Carta, N; Palumbo, Francesca; Raffo, Luigi | - | - |
| Coarse-grained reconfiguration: dataflow-based power management | 1-gen-2015 | Palumbo, Francesca; Sau, Carlo; Raffo, Luigi | IET COMPUTERS & DIGITAL TECHNIQUES | - |
| Concurrent hybrid switching for massively parallel systems-on-chip: The CYBER architecture | 1-gen-2012 | Palumbo, Francesca; Pani, Danilo; Congiu, Andrea; Raffo, Luigi | - | ACM |
| Design IP Faster: Introducing the C~ High-Level Language | 1-gen-2012 | Wipliez, M; Siret, N; Carta, N; Palumbo, Francesca; Raffo, Luigi | - | - |
| DSE and profiling of multi-context coarse-grained reconfigurable systems | 1-gen-2013 | Palumbo, Francesca; Sau, Carlo; Raffo, Luigi | - | IEEE |
| Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design | 1-gen-2016 | Sau, Carlo; Carta, N; Raffo, Luigi; Palumbo, Francesca | JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL, IMAGE, AND VIDEO TECHNOLOGY | - |
| Exploring custom heterogeneous MPSoCs for real-time neural signal decoding | 1-gen-2015 | Meloni, Paolo; Tuveri, Giuseppe; Pani, Danilo; Raffo, Luigi; Palumbo, Francesca | - | IEEE, Institute of Electrical and Electronics Engineers |
| A fast MPI-based parallel framework for cycle-accurate HDL multi-parametric simulations | 1-gen-2010 | Pani, Danilo; Palumbo, Francesca; Raffo, Luigi | INTERNATIONAL JOURNAL OF HIGH PERFORMANCE SYSTEMS ARCHITECTURE | - |
| Feasibility study and porting of the damped least square algorithm on FPGA | 1-gen-2020 | Sau, C.; Fanni, T.; Rubattu, C.; Fanni, L.; Raffo, L.; Palumbo, F. | IEEE ACCESS | - |
| An FPGA platform for real-time simulation of spiking neuronal networks | 1-gen-2017 | Pani, Danilo; Meloni, Paolo; Tuveri, Giuseppe; Palumbo, Francesca; Massobrio, Paolo; Raffo, Luigi | FRONTIERS IN NEUROSCIENCE | - |