Computing elements of CPSs must be flexible to ensure interoperability; and adaptive to cope with the evolving internal and external state, such as battery level and critical tasks. Cryptography is a common task needed in CPSs to guarantee private communication among different devices. In this work, we propose a reconfigurable FPGA accelerator for AES workloads with different key lengths. The accelerator architecture exploits tagged-dataflow models to support the concurrent execution of multiple threads on the same accelerator. This solution demonstrates to be more resource- and energy-efficient than a set of non-reconfigurable accelerators while keeping high performance and flexibility of execution.

A multithread AES accelerator for Cyber-Physical Systems

Ratto, Francesco
Primo
;
Raffo, Luigi;Palumbo, Francesca
2023-01-01

Abstract

Computing elements of CPSs must be flexible to ensure interoperability; and adaptive to cope with the evolving internal and external state, such as battery level and critical tasks. Cryptography is a common task needed in CPSs to guarantee private communication among different devices. In this work, we propose a reconfigurable FPGA accelerator for AES workloads with different key lengths. The accelerator architecture exploits tagged-dataflow models to support the concurrent execution of multiple threads on the same accelerator. This solution demonstrates to be more resource- and energy-efficient than a set of non-reconfigurable accelerators while keeping high performance and flexibility of execution.
2023
9798400701405
cryptography, reconfigurable computing, cyber-physical systems
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11584/373944
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