Adaptive CNN acceleration on FPGAs: closing the gap with state-of-the-art solutions

This paper presents a comparative study of a design flow for generating Convolutional Neural Network (CNN) accelerators on Field Programmable Gate Arrays (FPGAs), based on an extension of the Multi-Dataflow Composer (MDC) tool, against established frameworks: HLS4ML, FINN and Vitis AI. The proposed design flow explores a previously untapped area of the design space: runtime reconfigurable accelerators. By enabling runtime reconfigurability, it provides adaptivity support, filling a gap in current FPGA-based accelerator design options. The analysis focuses on the trade-offs and benefits of each approach, particularly regarding performance and adaptivity.