Domain-specific acceleration is now a “must” for all the computing spectrum, going from high performance computing to embedded systems. Unfortunately, system specialization is by nature a nightmare from the design productivity perspective. Nevertheless, in contexts where kernels to be accelerated are intrinsically streaming oriented, the combination of dataflow models of computation with Coarse-Grained Reconfigurable (CGR) architectures can be particularly handful. In this paper we introduce a novel methodology to assemble and characterize virtually reconfigurable accelerators based on dataflow and functional programming principles, capable of addressing design productivity issues for CGR accelerators. The main advantage of the proposed methodology is accurate IP-level latency predictability improving Design Space Exploration (DSE) when compared to state-of-the-art High-Level Synthesis (HLS).

Dataflow-functional high-level synthesis for coarse-grained reconfigurable accelerators

Rubattu, Claudio
;
Palumbo, Francesca;Sau, Carlo;Raffo, Luigi;
2019-01-01

Abstract

Domain-specific acceleration is now a “must” for all the computing spectrum, going from high performance computing to embedded systems. Unfortunately, system specialization is by nature a nightmare from the design productivity perspective. Nevertheless, in contexts where kernels to be accelerated are intrinsically streaming oriented, the combination of dataflow models of computation with Coarse-Grained Reconfigurable (CGR) architectures can be particularly handful. In this paper we introduce a novel methodology to assemble and characterize virtually reconfigurable accelerators based on dataflow and functional programming principles, capable of addressing design productivity issues for CGR accelerators. The main advantage of the proposed methodology is accurate IP-level latency predictability improving Design Space Exploration (DSE) when compared to state-of-the-art High-Level Synthesis (HLS).
2019
Caph just Aint Plain Hdl (CAPH); Coarse-grained reconfiguration (CGR); Dataflow (DF) models of computation (MoC); Design predictability; Design productivity; Field programmable gate array (FPGA); Functional programming; High-level synthesis (HLS); Multidataflow composer (MDC);
Acceleration; CAPH; Coarse-Grained Reconfiguration; Computer architecture; Dataflow MoC; Design Predictability; Design Productivity.; Field programmable gate arrays; FPGA; Functional Programming; Hardware; HLS; Kernel; MDC; Productivity; Tools; Control and Systems Engineering; Computer Science (all)
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11584/257978
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