In recent years, multilevel power converters have been gaining more and more interest in high voltage and high power conversion. Within this scenario, a very interesting approach lies in the use of semiconductors with different voltage ratings and different switching characteristics. For this aim both GTOs and IGBTs could be employed, but a better technological solution surely lies in the use of IGBTs only, with different voltage ratings. Optimized multilevel converter structures, based on the Multi-Point-Clamped (MPC) concept or on the series connection of H-bridge inverter could then be developed, exploiting the possibilities arising from the use of different voltage levels. The authors have developed an optimal modulation strategy that uses the redundant switching configurations of the MPC converter structure to achieve an increment of the output voltage levels number. The novel approach, that is here proposed, permits a reduction of the harmonic content of the voltage/current waveforms and an interesting optimization of the switching stresses of the power semiconductor devices.

Optimization of Harmonic Performances in Multilevel Converter Structures

DAMIANO, ALFONSO;MARONGIU, IGNAZIO;
1997-01-01

Abstract

In recent years, multilevel power converters have been gaining more and more interest in high voltage and high power conversion. Within this scenario, a very interesting approach lies in the use of semiconductors with different voltage ratings and different switching characteristics. For this aim both GTOs and IGBTs could be employed, but a better technological solution surely lies in the use of IGBTs only, with different voltage ratings. Optimized multilevel converter structures, based on the Multi-Point-Clamped (MPC) concept or on the series connection of H-bridge inverter could then be developed, exploiting the possibilities arising from the use of different voltage levels. The authors have developed an optimal modulation strategy that uses the redundant switching configurations of the MPC converter structure to achieve an increment of the output voltage levels number. The novel approach, that is here proposed, permits a reduction of the harmonic content of the voltage/current waveforms and an interesting optimization of the switching stresses of the power semiconductor devices.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11584/108871
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