This work presents an automatic power estimation and implementation flow for coarse-grained reconfigurable systems, capable of guiding designers towards the optimal implementation of power-efficient systems. The entire flow is assessed over the reconfigurable computing core of a dedicated image processing accelerator, targeting an ASIC 45 nm technology.

Coarse grain reconfiguration: Power estimation and management flow for hybrid gated systems

FANNI, TIZIANA;RAFFO, LUIGI
2016-01-01

Abstract

This work presents an automatic power estimation and implementation flow for coarse-grained reconfigurable systems, capable of guiding designers towards the optimal implementation of power-efficient systems. The entire flow is assessed over the reconfigurable computing core of a dedicated image processing accelerator, targeting an ASIC 45 nm technology.
2016
9781509037070
Reconfigurable hardware; Field programmable gate arrays (FPGA); Image processing; Reconfigurable architectures; Coarse-grained reconfigurable; Power efficient systems; Power estimations; Reconfigurable computing
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11584/223875
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