Studio e implementazione di strumenti per lo sviluppo software nei sistemi basati su FPGA.

Computer market becomes every day more performance-hungry. Nowadays microprocessor based systems are not able to relevant good performances in various application domains. The classic Von Neumann load/store architetture is suitable for some tasks, but seems to have serious scalability issues. To tackle these issues one of the current trend in the quest for additional execution speed, provides additional processing corees in the central processing unit and to parallelize the execution of as much of the software as possible. This paradigm has potential, but its effectiveness has been limited by the difficulties involved in parallelizing software that was written for sequential execution, resulting in cumbersome dependencies. These dependencies require extensive changes in the software design paradigms if this approach means to reach its full potential. On the other hand, reconfigurable devices have proven to be very scalable for a large class of applications and they offer potential application performance improvements beyond those predicted by Moore's Law. Among the different templates proposed in literature in the field or reconfigurable computing, Configurable System-on-a-Chip (CSoC) are emerging as a convincing trade-off between efficiency and flexibility. This kind of systems are often composed by one or more CPUs coupled with a Field Programmable Gate Array (FPGA), and it can be demonstrated that they can run applications two orders of magnitude faster than traditional on CPUs. This performance speedup with respect to microprocessors relies basically in the opportunity of using dedicated reconfigurable hardware to exploit the inherent parallelism of an algorithm. One of the key issues in using such systems is related to the software development activity. A programmer typically uses a high level language to implement its algorithms but, to exploit the full potential of a reconfigurable system, a deeper knowledge of the target architetture and of digital design techniques are needed. In this work two tools are developed and implemented to overcome these issues and allow the software developer to use its traditional development flow. The first one deals with code partitioning between CPU and FPGA. The tool takes as input an ANSI C application code and performs the following operations: (i) automatically identifies code fragments suitable for hardware implementation as specialized functional unite (ii) for all these segments a synthesizable code is generated and sent to a synthesis tool, (iii) from the synthesis results, the segments to be implemented on FPGA are selected (iv) bitstream to configure the FPGA and modified C code to be executed on the CPU are generated. In order to validate this tool, fit was applied to standard benchmarks obtaining, with respect to state of the art, an improvement of up to 250% in the accuracy of performances estimation related to the selected segments of code. The second tool developed, named eBug, is a debugging solution for software developed on the eMIPS dynamically-extensible processor. The off-chip portion of eBug is an application that performs tasks that would be too expensive or too inflexible to perform in hardware, such as implementing the communication protocols to interface to the client debuggers. The on-chip hardware portion of eBug is realized with a new approach: rather than being built into the base pipelined data path, it is a loadable logic module that uses the standard Extension interface of the processor. This accomplishes the three goals of area minimization and reuse, security in a general purpose, multi-user environment, and open-ended extensibility. When not in use, eBug is simply not present on the chip and its area is therefore reused. eBug solves the security issues normally created by a hardware-level debug module because only the process that owns the eBug Extension can be affected by a debugging session. As an Extension, eBug is not compiled into the basic processor design and this makes it easy to add new features without affecting the core eMIPS design. Leveraging the high-visibility extension interface of eMIPS, eBug can realize arbitrarily complex features for high-level monitoring. To show this feature hardware watchpoints support is transparently added to the initial, simpler design. It is also possible to interface eBug with other eMIPS extensions such as those generated by P2V to improve its capabilities. eBug was written in Verilog and is usable both with the Giano system simulator and on the Xilinx ML401 FPGA board.