Implantable recording/stimulating neural interface for peripheral nervous system

In recent years many researchers have focused their attention on the development and on the clinical experimentation of neural prosthesis [1] for hand amputees. Recent achievements in this field have made this challenge easier with the introduction of innovative biocompatible materials and the production of smart, light, artificial limbs characterized by lots of freedom degrees [2]. Despite such improvements, the communication between an implanted electrode and a prosthetic limb is still an open issue, due to long cables and cumbersome electronic equipments that typically separate them. In this contest it is very important the miniaturization of the electronic used to acquire the neural signals from efferent fibers of the Peripheral Nervous System (PNS) and to elicitate the afferent axons in order to restore the sensory feedback. Due to the weak amplitude of neural signals, this kind of design is particularly critical. Indeed neural signals are drowned in a noisy environment characterized by other biological electrical sources such as Electromyographic (EMG) interferences which have amplitudes many orders of magnitude greater than that of the neural signal and a bandwidth very close to them. Our group proposes an approach based on sigma delta converters that reduces the complexity in the analog (implanted) part and shifts the critical points on the digital side. A novel bidirectional interface for implantable PNS electrodes has been conceived, designed and is currently in the manufacturing phase after tape-out. In Fig.1 is depicted the system which is composed of two main blocks: the analog implantable CMOS circuit and the digital system controller, implemented on a FPGA. The recording unit (CMOS chip) contains a band-pass filter, a sigma-delta modulator and a current-output stimulator. The decimation module of the sigma/delta converter is located on an external digital device (implemented on a FPGA) which implements also a highly selective filter to separate the neural signal (800 Hz – 8kHz) from electromyographic interferences (100 Hz – 500 Hz). Such architecture was chosen to put in the implantable chip only the most critical analog modules while, at the same time, having a robust digital communication interface with the outside world. In this way, the digital communication protocol is more simple to implement and more robust to interferences and the implantable chip does not contain power hungry, sophisticated digital modules. The implantable device was designed on an austriamicrosystems 0.35um process. The chip layout is shown in Fig. 2. The chip contains 8 parallel readout channels and has a 4.1mm x 4.1mm die size. Several parameters (amplifier gain, opamp bandwidths, etc.) are programmable. Power consumption ranges from 20mW to 27.2mW depending on the operating mode. Each channel has an overall precision (taking into consideration noise and errors of all the blocks in the acquisition chain) of 10.4 bit. Fig. 3 shows the post-layout simulation results (including transient noise) for an input trace obtained from real measurements of an electrode implanted in a rat sciatic nerve. The original signal is largely affected by low-frequency noise (ECG and EMG) which is completely removed by the system. The simulation includes the off-chip decimation module.