DERIU, GIANFRANCO
DERIU, GIANFRANCO
Target-Aware Neural Architecture Search and Deployment for Keyword Spotting
2022-01-01 Busia, P.; Deriu, G.; Rinelli, L.; Chesta, C.; Raffo, L.; Meloni, P.
Task-Specific Automation in Deep Learning Processes
2021-01-01 Buchgeher, G.; Czech, G.; Ribeiro, A. S.; Kloihofer, W.; Meloni, P.; Busia, P.; Deriu, G.; Pintor, M.; Biggio, B.; Chesta, C.; Rinelli, L.; Solans, D.; Portela, M.
Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge
2020-01-01 Meloni, P.; Loi, D.; Deriu, G.; Carreras, M.; Conti, F.; Capotondi, A.; Rossi, D.
Optimizing Temporal Convolutional Network Inference on FPGA-Based Accelerators
2020-01-01 Carreras, M.; Deriu, G.; Raffo, L.; Benini, L.; Meloni, P.
Flexible acceleration of convolutions on FPGAs: Planning NEURAghe 2.0
2019-01-01 Carreras, M.; Deriu, G.; Meloni, P.
Optimization and deployment of CNNs at the Edge: The ALOHA experience
2019-01-01 Meloni, P.; Loi, D.; Busia, P.; Deriu, G.; Pimentel, A. D.; Sapra, D.; Stefanov, T.; Minakova, S.; Conti, F.; Benini, L.; Pintor, M.; Biggio, B.; Moser, B.; Shepelev, N.; Fragoulis, N.; Theodorakopoulos, I.; Masin, M.; Palumbo, F.
ALOHA: An architectural-aware framework for deep learning at the edge
2018-01-01 Meloni, P.; Loi, D.; Deriu, G.; Ripolles, O.; Solans, D.; Pimentel, A. D.; Sapra, D.; Pintor, Maura; Biggio, B.; Moser, B.; Shepeleva, N.; Stefanov, T.; Minakova, S.; Conti, F.; Benini, L.; Fragoulis, N.; Theodorakopoulos, I.; Masin, M.; Palumbo, F.
Architecture-aware design and implementation of CNN algorithms for embedded inference: The ALOHA project
2018-01-01 Meloni, P.; Loi, D.; Deriu, G.; Pimentel, A. D.; Saprat, D.; Pintor, M.; Biggio, B.; Ripolles, O.; Solans, D.; Conti, F.; Benini, L.; Stefanov, T.; Minakova, S.; Moser, B.; Shepeleva, N.; Masin, M.; Palumbo, F.; Fragoulis, N.; Theodorakopoulos, I.
Neuraghe: exploiting CPU-FPGA synergies for efficient and flexible CNN inference acceleration on zynQ SoCs
2018-01-01 Meloni, Paolo; Capotondi, Alessandro; Deriu, Gianfranco; Brian, Michele; Conti, Francesco; Rossi, Davide; Raffo, Luigi; Benini, Luca
A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC
2016-01-01 Meloni, Paolo; Deriu, Gianfranco; Conti, Francesco; Loi, Igor; Raffo, Luigi; Benini, Luca
Curbing the roofline: A scalable and flexible architecture for CNNs on FPGA
2016-01-01 Meloni, Paolo; Deriu, Gianfranco; Conti, Francesco; Loi, Igor; Raffo, Luigi; Benini, Luca
| Titolo | Data di pubblicazione | Autore(i) | Rivista | Editore |
|---|---|---|---|---|
| Target-Aware Neural Architecture Search and Deployment for Keyword Spotting | 1-gen-2022 | Busia, P.; Deriu, G.; Rinelli, L.; Chesta, C.; Raffo, L.; Meloni, P. | IEEE ACCESS | - |
| Task-Specific Automation in Deep Learning Processes | 1-gen-2021 | Buchgeher, G.; Czech, G.; Ribeiro, A. S.; Kloihofer, W.; Meloni, P.; Busia, P.; Deriu, G.; Pintor, M.; Biggio, B.; Chesta, C.; Rinelli, L.; Solans, D.; Portela, M. | - | Springer Science and Business Media Deutschland GmbH |
| Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge | 1-gen-2020 | Meloni, P.; Loi, D.; Deriu, G.; Carreras, M.; Conti, F.; Capotondi, A.; Rossi, D. | IEEE EMBEDDED SYSTEMS LETTERS | - |
| Optimizing Temporal Convolutional Network Inference on FPGA-Based Accelerators | 1-gen-2020 | Carreras, M.; Deriu, G.; Raffo, L.; Benini, L.; Meloni, P. | IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS | - |
| Flexible acceleration of convolutions on FPGAs: Planning NEURAghe 2.0 | 1-gen-2019 | Carreras, M.; Deriu, G.; Meloni, P. | - | CEUR-WS |
| Optimization and deployment of CNNs at the Edge: The ALOHA experience | 1-gen-2019 | Meloni, P.; Loi, D.; Busia, P.; Deriu, G.; Pimentel, A. D.; Sapra, D.; Stefanov, T.; Minakova, S.; Conti, F.; Benini, L.; Pintor, M.; Biggio, B.; Moser, B.; Shepelev, N.; Fragoulis, N.; Theodorakopoulos, I.; Masin, M.; Palumbo, F. | - | Association for Computing Machinery, Inc |
| ALOHA: An architectural-aware framework for deep learning at the edge | 1-gen-2018 | Meloni, P.; Loi, D.; Deriu, G.; Ripolles, O.; Solans, D.; Pimentel, A. D.; Sapra, D.; Pintor, Maura; Biggio, B.; Moser, B.; Shepeleva, N.; Stefanov, T.; Minakova, S.; Conti, F.; Benini, L.; Fragoulis, N.; Theodorakopoulos, I.; Masin, M.; Palumbo, F. | - | Association for Computing Machinery |
| Architecture-aware design and implementation of CNN algorithms for embedded inference: The ALOHA project | 1-gen-2018 | Meloni, P.; Loi, D.; Deriu, G.; Pimentel, A. D.; Saprat, D.; Pintor, M.; Biggio, B.; Ripolles, O.; Solans, D.; Conti, F.; Benini, L.; Stefanov, T.; Minakova, S.; Moser, B.; Shepeleva, N.; Masin, M.; Palumbo, F.; Fragoulis, N.; Theodorakopoulos, I. | - | Institute of Electrical and Electronics Engineers Inc. |
| Neuraghe: exploiting CPU-FPGA synergies for efficient and flexible CNN inference acceleration on zynQ SoCs | 1-gen-2018 | Meloni, Paolo; Capotondi, Alessandro; Deriu, Gianfranco; Brian, Michele; Conti, Francesco; Rossi, Davide; Raffo, Luigi; Benini, Luca | ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS | - |
| A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC | 1-gen-2016 | Meloni, Paolo; Deriu, Gianfranco; Conti, Francesco; Loi, Igor; Raffo, Luigi; Benini, Luca | - | Institute of Electrical and Electronics Engineers |
| Curbing the roofline: A scalable and flexible architecture for CNNs on FPGA | 1-gen-2016 | Meloni, Paolo; Deriu, Gianfranco; Conti, Francesco; Loi, Igor; Raffo, Luigi; Benini, Luca | - | Association for Computing Machinery, Inc |