A reconfigurable architecture oriented to low-power digital signal processing is presented, synthesised and tested on ETSI-GSM voice coding algorithms. An overall reduction of 44.6% cycles with respect to standard RISC processors is obtained. Such improvement together with locality and temporal correlation allows a reduction of power consumption.
|Titolo:||44.6% processing cycles reduction in GSM voice coding by low-power reconfigurable co-processor architecture|
|Data di pubblicazione:||2002|
|Tipologia:||1.1 Articolo in rivista|