In modern MPSoC architectures, programming to effectively exploit all the available resources becomes very challenging. Polyhedral Process Networks (PPN) are a known model of computation that represents a suitable solution for systematic mapping of parallel applications onto multiprocessor architectures. In previous works it has been shown that a given PPN program specification can be further analyzed and optimized, in order to meet the desired performance requirements. In this paper we present an online process splitting transformation that does not need a re-design of the communication patterns in network structure of the application. The novelty of our approach is that, differently from other compile-time approaches, the proposed transformation technique can be applied at run-time and followed, if needed, by the backward transformation. Using a FPGA-based MPSoC shared memory platform, we present an evaluation of the achievable performance improvements. We also discuss the overhead caused by the introduction of the run-time transformation support.

Online process transformation for polyhedral process networks in shared-memory MPSoCs

MELONI, PAOLO;TUVERI, GIUSEPPE;RAFFO, LUIGI;
2014-01-01

Abstract

In modern MPSoC architectures, programming to effectively exploit all the available resources becomes very challenging. Polyhedral Process Networks (PPN) are a known model of computation that represents a suitable solution for systematic mapping of parallel applications onto multiprocessor architectures. In previous works it has been shown that a given PPN program specification can be further analyzed and optimized, in order to meet the desired performance requirements. In this paper we present an online process splitting transformation that does not need a re-design of the communication patterns in network structure of the application. The novelty of our approach is that, differently from other compile-time approaches, the proposed transformation technique can be applied at run-time and followed, if needed, by the backward transformation. Using a FPGA-based MPSoC shared memory platform, we present an evaluation of the achievable performance improvements. We also discuss the overhead caused by the introduction of the run-time transformation support.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11584/105265
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