In modern MPSoC architectures, programming to effectively exploit all the available resources becomes very challenging. Polyhedral Process Networks (PPN) are a known model of computation that represents a suitable solution for system- Atic mapping of parallel applications onto multiprocessor ar- chitectures. In previous works it has been shown that a given PPN program specification can be further analyzed and op- Timized, in order to meet the desired performance require- ments. In this paper we present an online process splitting transformation that does not need a re-design of the com- munication patterns in network structure of the application. The novelty of our approach is that, differently from other compile- Time approaches, the proposed transformation tech- nique can be applied at run- Time and followed, if needed, by the backward transformation. Using a FPGA-based MPSoC shared memory platform, we present an evaluation of the achievable performance improvements. We also discuss the overhead caused by the introduction of the run- Time trans- formation support.
A stream buffer mechanism for pervasive splitting transformations on polyhedral process networks
MELONI, PAOLO;TUVERI, GIUSEPPE;RAFFO, LUIGI;
2014-01-01
Abstract
In modern MPSoC architectures, programming to effectively exploit all the available resources becomes very challenging. Polyhedral Process Networks (PPN) are a known model of computation that represents a suitable solution for system- Atic mapping of parallel applications onto multiprocessor ar- chitectures. In previous works it has been shown that a given PPN program specification can be further analyzed and op- Timized, in order to meet the desired performance require- ments. In this paper we present an online process splitting transformation that does not need a re-design of the com- munication patterns in network structure of the application. The novelty of our approach is that, differently from other compile- Time approaches, the proposed transformation tech- nique can be applied at run- Time and followed, if needed, by the backward transformation. Using a FPGA-based MPSoC shared memory platform, we present an evaluation of the achievable performance improvements. We also discuss the overhead caused by the introduction of the run- Time trans- formation support.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.