Redundancy in the output code as an instrument to reduce the impact of nonidealities in different architectures of two-step analog to digital converters (ADC) is investigated. The CRZ converters, which are the converters obtained from the conventional CR architecture with addition of Z extra decision levels, are formalized and compared with the RSD converter. Two distinct models are proposed to investigate separately, by means of system level simulations, the impact of each source of error: the behavioral model and the circuit model. The first one is intended to give an intuitive understanding of how redundancy improves the output response of this class of converters, while the latter is introduced to find, at an early design stage, the optimum sizing of passive components meeting a given resolution. Simulation results from both models are discussed and the different performances of the various converters are evaluated with respect to power, area, and effective resolution.

Modeling, evaluation and comparison of CRZ and RSD redundant architectures for two-step A/D converters

BARBARO, MASSIMO;
2008

Abstract

Redundancy in the output code as an instrument to reduce the impact of nonidealities in different architectures of two-step analog to digital converters (ADC) is investigated. The CRZ converters, which are the converters obtained from the conventional CR architecture with addition of Z extra decision levels, are formalized and compared with the RSD converter. Two distinct models are proposed to investigate separately, by means of system level simulations, the impact of each source of error: the behavioral model and the circuit model. The first one is intended to give an intuitive understanding of how redundancy improves the output response of this class of converters, while the latter is introduced to find, at an early design stage, the optimum sizing of passive components meeting a given resolution. Simulation results from both models are discussed and the different performances of the various converters are evaluated with respect to power, area, and effective resolution.
Analog-to-digital converters; CRZ architecture; Redundant signed digit (RSD) architecture
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11584/17932
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