In this brief, a novel pseudo resistor bias scheme capable of achieving improved performances against process parameter variations is presented. The use of a matched structure allows for achieving a simulated statistical variation σ/μ one order of magnitude better than conventional bias schemes proposed in the literature. The entire circuit was designed to be able to emulate a tunable resistor whose resistance could be digitally set in the range of 400 MΩ-90 GΩ. The design of a very low frequency bandpass filter (BPF) for biopotential recording was also covered as a suitable application. The tunability offered by the bias scheme was employed, in this case, to realize a high-pass cutoff frequency variable in the range of 10 Hz-2 kHz. An integrated circuit including eight acquisition channels, each of which is composed of the designed BPF and a conventional 10-bit analog-to-digital converter, was finally realized in a CMOS 0.35-μm process. The chip was successfully tested showing a measured σ/μ variation of the high-pass cutoff frequency equal to 0.13 when different channels on the same die are considered.

A precision pseudo resistor bias scheme for the design of very large time constant filters

PUDDU, ROBERTO;CARBONI, CATERINA;BISONI, LORENZO;BARABINO, GIANLUCA;PANI, DANILO;RAFFO, LUIGI;BARBARO, MASSIMO
2017

Abstract

In this brief, a novel pseudo resistor bias scheme capable of achieving improved performances against process parameter variations is presented. The use of a matched structure allows for achieving a simulated statistical variation σ/μ one order of magnitude better than conventional bias schemes proposed in the literature. The entire circuit was designed to be able to emulate a tunable resistor whose resistance could be digitally set in the range of 400 MΩ-90 GΩ. The design of a very low frequency bandpass filter (BPF) for biopotential recording was also covered as a suitable application. The tunability offered by the bias scheme was employed, in this case, to realize a high-pass cutoff frequency variable in the range of 10 Hz-2 kHz. An integrated circuit including eight acquisition channels, each of which is composed of the designed BPF and a conventional 10-bit analog-to-digital converter, was finally realized in a CMOS 0.35-μm process. The chip was successfully tested showing a measured σ/μ variation of the high-pass cutoff frequency equal to 0.13 when different channels on the same die are considered.
neural recording; process variations; pseudo resistor (PR); very low frequency filter; Electrical and Electronic Engineering
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11584/182215
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