Applications and hardware complexity management in modern systems tend to collide with efficient resource and power balance. Therefore, dedicated and power-aware design frameworks are necessary to implement efficient multi-functional runtime reconfigurable signal processing platforms. In this work, we adopt dataflow specifications as a starting point to challenge power minimization.

Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy

PALUMBO, FRANCESCA;SAU, CARLO;RAFFO, LUIGI
2014

Abstract

Applications and hardware complexity management in modern systems tend to collide with efficient resource and power balance. Therefore, dedicated and power-aware design frameworks are necessary to implement efficient multi-functional runtime reconfigurable signal processing platforms. In this work, we adopt dataflow specifications as a starting point to challenge power minimization.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11584/109738
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