The design of embedded systems for neuroprosthetic applications represents an important challenge to be faced in electronic bioengineering. One of the key research problems is decoding the information encoded in neural signals to extract the patient's motion intention. How to implement a highly-portable and reliable integrated solution is still an open issue. In this paper, we investigate the possibility of adopting the MPSoC paradigm in this application domain, presenting a design space exploration that evaluates different custom MPSoC embedded architectures, implementing an on-line neural signal decoding algorithm. The evaluated design points feature different mappings of parallel software tasks onto customized ASIP processing cores. Experimental results, obtained by FPGA-based prototyping, assess the performance and hardware-related costs of the considered configurations. The clock frequency needed to respect real-time constraints was reduced to 22 MHz, making a step further towards the exploitation of custom heterogeneous MPSoCs for ultra-low power biomedical signal processing.

Exploring custom heterogeneous MPSoCs for real-time neural signal decoding

MELONI, PAOLO;TUVERI, GIUSEPPE;PANI, DANILO;RAFFO, LUIGI;PALUMBO, FRANCESCA
2015

Abstract

The design of embedded systems for neuroprosthetic applications represents an important challenge to be faced in electronic bioengineering. One of the key research problems is decoding the information encoded in neural signals to extract the patient's motion intention. How to implement a highly-portable and reliable integrated solution is still an open issue. In this paper, we investigate the possibility of adopting the MPSoC paradigm in this application domain, presenting a design space exploration that evaluates different custom MPSoC embedded architectures, implementing an on-line neural signal decoding algorithm. The evaluated design points feature different mappings of parallel software tasks onto customized ASIP processing cores. Experimental results, obtained by FPGA-based prototyping, assess the performance and hardware-related costs of the considered configurations. The clock frequency needed to respect real-time constraints was reduced to 22 MHz, making a step further towards the exploitation of custom heterogeneous MPSoCs for ultra-low power biomedical signal processing.
979-109227910-8
Sorting; Program processors; Decoding; Real-time systems; Computer architecture; Noise reduction; Algorithm design and analysis
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11584/137270
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