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EnglishPower reduction is one of the biggest challenges in modern systems and tends to become a severe issue dealing with complex scenarios. To provide high-performance and exi-bility, designers often opt for coarse-grained reconfigurable (CGR) systems. Nevertheless, these systems require specific attention to the power problem, since large set of resources may be underutilized while computing a certain task. This paper focuses on this issue. Targeting CGR devices, we propose a way to model in advance power and clock gat-ing costs on the basis of the functional, technological and architectural parameters of the baseline CGR system. The proposed ow guides designers towards optimal implemen-Tations, saving designer effort and time.
| Titolo: | Power and clock gating modelling in coarse grained reconfigurable systems | |
| Autori: | ||
| Data di pubblicazione: | 2016 | |
| Handle: | http://hdl.handle.net/11584/178559 | |
| ISBN: | 978-145034128-8 | |
| Tipologia: | 4.1 Contributo in Atti di convegno |
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http://hdl.handle.net/11584/178559
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