Power reduction is one of the biggest challenges in modern systems and tends to become a severe issue dealing with complex scenarios. To provide high-performance and exi-bility, designers often opt for coarse-grained reconfigurable (CGR) systems. Nevertheless, these systems require specific attention to the power problem, since large set of resources may be underutilized while computing a certain task. This paper focuses on this issue. Targeting CGR devices, we propose a way to model in advance power and clock gat-ing costs on the basis of the functional, technological and architectural parameters of the baseline CGR system. The proposed ow guides designers towards optimal implemen-Tations, saving designer effort and time.
|Titolo:||Power and clock gating modelling in coarse grained reconfigurable systems|
|Data di pubblicazione:||2016|
|Tipologia:||4.1 Contributo in Atti di convegno|