This paper focuses on howto efficiently reduce power consumption in coarse-grained reconfigurable designs, to allowtheir effective adoption in heterogeneous architectures supporting and accelerating complex and highly variablemultifunctional applications.We propose a design flow for this kind of architectures that, besides their automatic customization, is also capable of determining their optimal power management support. Power and clock gating implementation costs are estimated in advance, before their physical implementation, on the basis of the functional, technological, and architectural parameters of the baseline design. Experimental results, on 90 and 45 nm CMOS technologies, demonstrate that the proposed approach guides the designer towards optimal implementation.

Modelling and automated implementation of optimal power saving strategies in coarse-grained reconfigurable architectures

PALUMBO, FRANCESCA;FANNI, TIZIANA;SAU, CARLO;MELONI, PAOLO;RAFFO, LUIGI
2016

Abstract

This paper focuses on howto efficiently reduce power consumption in coarse-grained reconfigurable designs, to allowtheir effective adoption in heterogeneous architectures supporting and accelerating complex and highly variablemultifunctional applications.We propose a design flow for this kind of architectures that, besides their automatic customization, is also capable of determining their optimal power management support. Power and clock gating implementation costs are estimated in advance, before their physical implementation, on the basis of the functional, technological, and architectural parameters of the baseline design. Experimental results, on 90 and 45 nm CMOS technologies, demonstrate that the proposed approach guides the designer towards optimal implementation.
Signal Processing; Computer Science (all); Electrical and Electronic Engineering
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11584/195792
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