UNICA IRIS Institutional Research Information System

MELONI, PAOLO
 Distribuzione geografica
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Continente #
EU - Europa 110.483
NA - Nord America 5.591
AS - Asia 2.191
SA - Sud America 271
AF - Africa 34
OC - Oceania 7
Continente sconosciuto - Info sul continente non disponibili 5
Totale 118.582
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Nazione #
IT - Italia 109.137
US - Stati Uniti d'America 5.483
CN - Cina 940
SG - Singapore 863
SE - Svezia 339
UA - Ucraina 332
BR - Brasile 231
DE - Germania 197
FI - Finlandia 130
GB - Regno Unito 115
VN - Vietnam 111
CA - Canada 79
FR - Francia 64
IN - India 46
KR - Corea 45
HK - Hong Kong 38
NL - Olanda 26
PL - Polonia 25
MX - Messico 22
TR - Turchia 21
ES - Italia 19
BE - Belgio 18
JP - Giappone 17
MA - Marocco 14
AR - Argentina 13
AT - Austria 11
DK - Danimarca 11
IQ - Iraq 11
ZA - Sudafrica 11
GR - Grecia 10
TW - Taiwan 10
BD - Bangladesh 9
IR - Iran 9
LT - Lituania 9
LV - Lettonia 9
RU - Federazione Russa 9
CO - Colombia 8
KG - Kirghizistan 7
SA - Arabia Saudita 7
UZ - Uzbekistan 7
CZ - Repubblica Ceca 5
EC - Ecuador 5
EU - Europa 5
ID - Indonesia 5
PH - Filippine 5
AE - Emirati Arabi Uniti 4
IL - Israele 4
KZ - Kazakistan 4
PK - Pakistan 4
AU - Australia 3
AZ - Azerbaigian 3
CL - Cile 3
IE - Irlanda 3
JO - Giordania 3
LK - Sri Lanka 3
LU - Lussemburgo 3
MY - Malesia 3
UY - Uruguay 3
VE - Venezuela 3
AM - Armenia 2
CG - Congo 2
CH - Svizzera 2
CY - Cipro 2
DO - Repubblica Dominicana 2
EE - Estonia 2
GE - Georgia 2
JM - Giamaica 2
KE - Kenya 2
MN - Mongolia 2
NO - Norvegia 2
NZ - Nuova Zelanda 2
PE - Perù 2
PT - Portogallo 2
PY - Paraguay 2
BO - Bolivia 1
BY - Bielorussia 1
CR - Costa Rica 1
ET - Etiopia 1
HN - Honduras 1
IS - Islanda 1
LA - Repubblica Popolare Democratica del Laos 1
MG - Madagascar 1
NR - Nauru 1
OM - Oman 1
PR - Porto Rico 1
SC - Seychelles 1
SK - Slovacchia (Repubblica Slovacca) 1
SN - Senegal 1
TH - Thailandia 1
TJ - Tagikistan 1
TN - Tunisia 1
TV - Tuvalu 1
Totale 118.582
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Città #
Cagliari 105.275
Uta 3.491
Fairfield 599
Ashburn 526
Singapore 409
Chandler 388
Woodbridge 353
Dallas 330
Houston 297
Seattle 256
Wilmington 253
Nyköping 240
Boardman 229
Cambridge 229
Ann Arbor 218
Beijing 196
Jacksonville 166
Los Angeles 131
Dearborn 104
Shanghai 101
Santa Clara 94
Nanjing 85
Hefei 74
Helsinki 68
Chicago 66
Buffalo 56
The Dalles 55
Guangzhou 54
Boston 49
Ottawa 46
Seoul 41
New York 40
San Diego 38
Munich 34
Ho Chi Minh City 32
Sassari 29
Hong Kong 28
Frankfurt am Main 26
Redwood City 25
Rome 23
Dong Ket 22
Nanchang 22
Redondo Beach 22
Salt Lake City 22
Warsaw 22
Washington 22
Milan 20
Jiaxing 19
Nuremberg 19
Atlanta 18
Brussels 18
Council Bluffs 18
Tianjin 18
Hanoi 17
Jinan 17
London 16
Brooklyn 15
Changsha 15
Kunming 13
Shenyang 13
Lauterbourg 12
Toronto 12
Brasília 11
Denver 11
Elk Grove Village 11
Montreal 11
Mountain View 11
Tokyo 11
Hangzhou 10
Orange 10
Pune 10
Belo Horizonte 9
Düsseldorf 9
Mexico City 9
Phoenix 9
Riga 9
Tampa 9
Turku 9
Amsterdam 8
Casablanca 8
Copenhagen 8
Johannesburg 8
Lappeenranta 8
Rio de Janeiro 8
San Francisco 8
Shenzhen 8
São Paulo 8
Taipei 8
Ankara 7
Bishkek 7
Hebei 7
Indiana 7
Southend 7
Baghdad 6
Biên Hòa 6
Manchester 6
Ningbo 6
Poplar 6
Sterling 6
Stockholm 6
Totale 115.462
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Nome #
MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation 3.369
Automated Design Flow for Multi-Functional Dataflow-Based Platforms 3.136
An FPGA platform for real-time simulation of spiking neuronal networks 3.031
FPGA-Based Emulation Support for Design Space Exploration 2.837
Real-time neural signals decoding onto off-the-shelf DSP processors for neuroprosthetic applications 2.801
Neuraghe: exploiting CPU-FPGA synergies for efficient and flexible CNN inference acceleration on zynQ SoCs 2.618
Optimization and deployment of CNNs at the Edge: The ALOHA experience 2.610
Modelling and automated implementation of optimal power saving strategies in coarse-grained reconfigurable architectures 2.540
Power modelling for saving strategies in coarse grained reconfigurable systems 2.527
System adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project approach 2.518
Power and clock gating modelling in coarse grained reconfigurable systems 2.487
Exploring custom heterogeneous MPSoCs for real-time neural signal decoding 2.475
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing 2.394
Exploiting binary translation for fast ASIP design space exploration on FPGAs 2.356
ALOHA: An architectural-aware framework for deep learning at the edge 2.266
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms 2.259
Reconfigurable Coprocessors Synthesis in the MPEG-RVC Domain 2.248
Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy 2.214
ASAM: Automatic architecture synthesis and application mapping 2.191
Curbing the roofline: A scalable and flexible architecture for CNNs on FPGA 2.158
Exploiting All Programmable SoCs in Neural Signal Analysis: A Closed-Loop Control for Large-Scale CMOS Multielectrode Arrays 2.147
A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC 1.941
Runtime Energy versus Quality Tuning in Motion Compensation Filters for HEVC 1.888
A stream buffer mechanism for pervasive splitting transformations on polyhedral process networks 1.887
Online process transformation for polyhedral process networks in shared-memory MPSoCs 1.857
ALOHA: A Unified Platform-Aware Evaluation Method for CNNs Execution on Heterogeneous Systems at the Edge 1.835
A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project 1.789
SS-design: Dataflow-based design of coarse-grained: Reconfigurable platforms reconfigurable platform composer tool project - Extended abstract 1.770
Sustainable water management in quality wine-making 1.754
Architecture-aware design and implementation of CNN algorithms for embedded inference: The ALOHA project 1.677
A low overhead self-adaptation technique for KPN applications on NoC-based MPSoCs 1.668
On-the-fly adaptivity for process networks over shared-memory platforms 1.641
A runtime adaptive H.264 video-decoding MPSoC platform 1.632
Enabling fast ASIP design space exploration: An FPGA-based runtime reconfigurable prototyper 1.623
null 1.597
ASAM: Automatic Architecture Synthesis and Application Mapping 1.593
Feasibility study of real-time spiking neural network simulations on a swarm intelligence based digital architecture 1.571
Adaptivity support for MPSoCs based on process migration in polyhedral process networks 1.565
null 1.460
null 1.198
ZyON: Enabling Spike Sorting on APSoC-Based Signal Processors for High-Density Microelectrode Arrays 1.128
Routing Aware Switch Hardware Customization for Networks on Chips 1.095
Area and Power Modeling for Networks-on-Chip with Layout Awareness 1.074
Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems 1.053
A Bandwidth-Efficient Emulator of Biologically-Relevant Spiking Neural Networks on FPGA 1.051
Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper 1.033
Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures 998
Methods for hardware reduction and overall performance improvement in communication systems 984
An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures 963
Synthesis of predictable networks-on-chip-based interconnect Architectures for chip multiprocessors 960
Optimizing the serialization factor in Networks-on-Chip: a case of study 945
On the impact of serializatioin on the cache performances in Network-on-Chip based MPSoCs 886
An FPGA Research Environment for Rapid MPSoC Exploration 885
Designing Routing and Message-Dependent Deadlock Free Networks on Chips 882
Area and Power Modeling Methodologies for Networks-on-Chip 881
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs 873
Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness 856
Networks on Chips: A Synthesis Perspective 849
Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge 839
NoC Design and Implementation in 65nm Technology 830
Designing Application-Specific Networks on Chips with Floorplan Information 818
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs 812
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems-on-Chips 801
Dynamic Pruning for Parsimonious CNN Inference on Embedded Systems 797
An Adaptive Cognitive Sensor Node for ECG Monitoring in the Internet of Medical Things 747
On-FPGA Spiking Neural Networks for End-to-End Neural Decoding 733
A custom MPSoC architecture with integrated power management for real-time neural signal decoding 710
Flexible acceleration of convolutions on FPGAs: Planning NEURAghe 2.0 679
Demo: Reconfigurable Platform Composer Tool 678
Runtime adaptive iomt node on multi-core processor platform 658
Runtime-adaptive cognitive IoT nodes 635
An Adaptable Cognitive Microcontroller Node for Fitness Activity Recognition 627
Target-Aware Neural Architecture Search and Deployment for Keyword Spotting 611
An Automated Design Flow for Adaptive Neural Network Hardware Accelerators 610
On-FPGA real-time processing of biological signals from high-density MEAs: A design space exploration 604
Design and optimization techniques for VLSI Network on Chip architectures 583
Task-Specific Automation in Deep Learning Processes 520
Reducing False Alarms in Wearable Seizure Detection with EEGformer: A Compact Transformer Model for MCUs 463
EEGformer: Transformer-Based Epilepsy Detection on Raw EEG Traces for Low-Channel-Count Wearable Continuous Monitoring Devices 436
Real-Time sEMG Processing with Spiking Neural Networks on a Low-Power 5K-LUT FPGA 356
Optimizing Temporal Convolutional Network Inference on FPGA-Based Accelerators 311
A tiny transformer for low-power arrhythmia classification on microcontrollers 264
null 199
Design of an AI-driven Architecture with Cobots for Digital Transformation to Enhance Quality Control in the Food Industry 180
SYNtzulu: A Tiny RISC-V-Controlled SNN Processor for Real-Time Sensor Data Analysis on Low-Power FPGAs 161
A Runtime-Adaptive Cognitive IoT Node for Healthcare Monitoring 154
null 122
On-FPGA Spiking Neural Networks for Integrated Near-Sensor ECG Analysis 116
null 103
Low-Power FPGA-based Spiking Neural Networks for Real-Time Decoding of Intracortical Neural Activity 93
Wearable Epilepsy Seizure Detection on FPGA with Spiking Neural Networks 69
ESTU: Enabling Spiking Transformers on Ultra-Low-Power FPGAs 17
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs 14
CNN hardware acceleration on a low-power and low-cost APSoC 2
Totale 118.876
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Categoria #
all - tutte 149.808
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 149.808
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/202110.075 0 0 0 0 0 2.486 2.403 1.317 790 1.166 1.156 757
2021/20225.803 742 529 197 341 502 472 217 150 462 879 719 593
2022/20239.239 609 1.155 926 944 811 1.032 508 679 616 582 941 436
2023/202410.968 568 380 496 545 1.047 1.628 1.740 696 474 831 1.488 1.075
2024/202527.861 3.278 10.616 3.119 3.074 2.788 2.477 1.299 131 207 199 412 261
2025/20262.818 485 272 741 444 529 347 0 0 0 0 0 0
Totale 118.876