UNICA IRIS Institutional Research Information System

MELONI, PAOLO
 Distribuzione geografica
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Continente #
EU - Europa 112.726
NA - Nord America 6.250
AS - Asia 3.009
SA - Sud America 357
AF - Africa 63
OC - Oceania 9
Continente sconosciuto - Info sul continente non disponibili 5
Totale 122.419
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Nazione #
IT - Italia 111.200
US - Stati Uniti d'America 6.130
SG - Singapore 1.153
CN - Cina 1.096
SE - Svezia 341
UA - Ucraina 336
BR - Brasile 271
VN - Vietnam 239
DE - Germania 211
FI - Finlandia 168
FR - Francia 143
GB - Regno Unito 130
HK - Hong Kong 115
CA - Canada 84
IN - India 83
KR - Corea 45
BD - Bangladesh 32
NL - Olanda 32
TR - Turchia 32
PL - Polonia 26
MX - Messico 25
AR - Argentina 24
IQ - Iraq 24
ES - Italia 23
JP - Giappone 23
BE - Belgio 19
CO - Colombia 18
ZA - Sudafrica 18
PK - Pakistan 17
TW - Taiwan 16
MA - Marocco 15
SA - Arabia Saudita 14
PH - Filippine 13
AT - Austria 12
RU - Federazione Russa 12
UZ - Uzbekistan 12
VE - Venezuela 12
DK - Danimarca 11
GR - Grecia 11
CL - Cile 10
LT - Lituania 10
LV - Lettonia 10
EC - Ecuador 9
ID - Indonesia 9
IR - Iran 9
TN - Tunisia 9
KG - Kirghizistan 7
MY - Malesia 7
NP - Nepal 7
AZ - Azerbaigian 6
IL - Israele 6
AE - Emirati Arabi Uniti 5
AU - Australia 5
CZ - Repubblica Ceca 5
ET - Etiopia 5
EU - Europa 5
JO - Giordania 5
IE - Irlanda 4
JM - Giamaica 4
KZ - Kazakistan 4
MN - Mongolia 4
OM - Oman 4
PE - Perù 4
PT - Portogallo 4
BO - Bolivia 3
CH - Svizzera 3
DZ - Algeria 3
KE - Kenya 3
LK - Sri Lanka 3
LU - Lussemburgo 3
PY - Paraguay 3
TH - Thailandia 3
UY - Uruguay 3
AM - Armenia 2
BY - Bielorussia 2
CG - Congo 2
CR - Costa Rica 2
CY - Cipro 2
DO - Repubblica Dominicana 2
EE - Estonia 2
GE - Georgia 2
HN - Honduras 2
KW - Kuwait 2
NO - Norvegia 2
NZ - Nuova Zelanda 2
PS - Palestinian Territory 2
RO - Romania 2
AO - Angola 1
BG - Bulgaria 1
IS - Islanda 1
KH - Cambogia 1
LA - Repubblica Popolare Democratica del Laos 1
LB - Libano 1
LY - Libia 1
MG - Madagascar 1
MU - Mauritius 1
NG - Nigeria 1
NR - Nauru 1
PR - Porto Rico 1
QA - Qatar 1
Totale 122.411
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Città #
Cagliari 107.307
Uta 3.491
Singapore 645
Ashburn 600
Fairfield 599
Chandler 388
San Jose 368
Woodbridge 353
Dallas 331
Houston 297
Seattle 256
Wilmington 253
Nyköping 240
Boardman 230
Cambridge 229
Ann Arbor 218
Beijing 210
Jacksonville 167
Los Angeles 163
Helsinki 105
Shanghai 105
Dearborn 104
Santa Clara 100
Hong Kong 99
Nanjing 85
Ho Chi Minh City 77
Lauterbourg 77
The Dalles 77
Hefei 74
Chicago 68
Council Bluffs 63
Guangzhou 58
Buffalo 57
New York 51
Boston 50
Hanoi 48
Ottawa 46
Seoul 41
San Diego 40
Munich 34
Frankfurt am Main 30
Rome 29
Sassari 29
Redwood City 25
Milan 24
Warsaw 23
Washington 23
Dong Ket 22
Nanchang 22
Redondo Beach 22
Salt Lake City 22
Tianjin 21
Nuremberg 20
Atlanta 19
Jiaxing 19
London 19
Brussels 18
Jinan 18
Orem 18
Brooklyn 15
Changsha 15
Chennai 15
Tokyo 15
Shenyang 14
Denver 13
Kunming 13
Montreal 13
São Paulo 13
Taipei 13
Toronto 13
Amsterdam 12
Brasília 12
Hangzhou 12
Pune 12
Baghdad 11
Elk Grove Village 11
Johannesburg 11
Mountain View 11
Phoenix 11
Shenzhen 11
Belo Horizonte 10
Orange 10
Riga 10
Düsseldorf 9
Haiphong 9
Lappeenranta 9
Mexico City 9
San Francisco 9
Tampa 9
Tashkent 9
Turku 9
Casablanca 8
Copenhagen 8
Da Nang 8
Istanbul 8
Rio de Janeiro 8
Ankara 7
Bishkek 7
Biên Hòa 7
Hebei 7
Totale 118.663
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Nome #
MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation 3.401
Automated Design Flow for Multi-Functional Dataflow-Based Platforms 3.169
An FPGA platform for real-time simulation of spiking neuronal networks 3.060
FPGA-Based Emulation Support for Design Space Exploration 2.870
Real-time neural signals decoding onto off-the-shelf DSP processors for neuroprosthetic applications 2.847
Neuraghe: exploiting CPU-FPGA synergies for efficient and flexible CNN inference acceleration on zynQ SoCs 2.655
Optimization and deployment of CNNs at the Edge: The ALOHA experience 2.652
Modelling and automated implementation of optimal power saving strategies in coarse-grained reconfigurable architectures 2.604
Power modelling for saving strategies in coarse grained reconfigurable systems 2.577
System adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project approach 2.560
Power and clock gating modelling in coarse grained reconfigurable systems 2.526
Exploring custom heterogeneous MPSoCs for real-time neural signal decoding 2.523
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing 2.456
Exploiting binary translation for fast ASIP design space exploration on FPGAs 2.396
ALOHA: An architectural-aware framework for deep learning at the edge 2.309
Reconfigurable Coprocessors Synthesis in the MPEG-RVC Domain 2.298
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms 2.290
Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy 2.253
ASAM: Automatic architecture synthesis and application mapping 2.239
Curbing the roofline: A scalable and flexible architecture for CNNs on FPGA 2.199
Exploiting All Programmable SoCs in Neural Signal Analysis: A Closed-Loop Control for Large-Scale CMOS Multielectrode Arrays 2.195
A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC 1.971
A stream buffer mechanism for pervasive splitting transformations on polyhedral process networks 1.953
Runtime Energy versus Quality Tuning in Motion Compensation Filters for HEVC 1.930
Online process transformation for polyhedral process networks in shared-memory MPSoCs 1.892
ALOHA: A Unified Platform-Aware Evaluation Method for CNNs Execution on Heterogeneous Systems at the Edge 1.875
A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project 1.836
Sustainable water management in quality wine-making 1.827
SS-design: Dataflow-based design of coarse-grained: Reconfigurable platforms reconfigurable platform composer tool project - Extended abstract 1.817
Architecture-aware design and implementation of CNN algorithms for embedded inference: The ALOHA project 1.719
A low overhead self-adaptation technique for KPN applications on NoC-based MPSoCs 1.712
On-the-fly adaptivity for process networks over shared-memory platforms 1.697
A runtime adaptive H.264 video-decoding MPSoC platform 1.667
Enabling fast ASIP design space exploration: An FPGA-based runtime reconfigurable prototyper 1.655
ASAM: Automatic Architecture Synthesis and Application Mapping 1.634
Adaptivity support for MPSoCs based on process migration in polyhedral process networks 1.617
null 1.597
Feasibility study of real-time spiking neural network simulations on a swarm intelligence based digital architecture 1.571
null 1.460
null 1.198
ZyON: Enabling Spike Sorting on APSoC-Based Signal Processors for High-Density Microelectrode Arrays 1.167
Routing Aware Switch Hardware Customization for Networks on Chips 1.125
Area and Power Modeling for Networks-on-Chip with Layout Awareness 1.119
A Bandwidth-Efficient Emulator of Biologically-Relevant Spiking Neural Networks on FPGA 1.101
Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems 1.086
Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper 1.060
Methods for hardware reduction and overall performance improvement in communication systems 1.032
Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures 1.028
An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures 1.002
Synthesis of predictable networks-on-chip-based interconnect Architectures for chip multiprocessors 991
Optimizing the serialization factor in Networks-on-Chip: a case of study 989
Area and Power Modeling Methodologies for Networks-on-Chip 924
On the impact of serializatioin on the cache performances in Network-on-Chip based MPSoCs 918
An FPGA Research Environment for Rapid MPSoC Exploration 916
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs 915
Designing Routing and Message-Dependent Deadlock Free Networks on Chips 908
Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness 904
Networks on Chips: A Synthesis Perspective 882
Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge 881
NoC Design and Implementation in 65nm Technology 865
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs 854
Designing Application-Specific Networks on Chips with Floorplan Information 852
Dynamic Pruning for Parsimonious CNN Inference on Embedded Systems 844
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems-on-Chips 835
On-FPGA Spiking Neural Networks for End-to-End Neural Decoding 796
An Adaptive Cognitive Sensor Node for ECG Monitoring in the Internet of Medical Things 790
A custom MPSoC architecture with integrated power management for real-time neural signal decoding 753
Flexible acceleration of convolutions on FPGAs: Planning NEURAghe 2.0 732
Demo: Reconfigurable Platform Composer Tool 721
Runtime adaptive iomt node on multi-core processor platform 699
An Adaptable Cognitive Microcontroller Node for Fitness Activity Recognition 684
Runtime-adaptive cognitive IoT nodes 684
An Automated Design Flow for Adaptive Neural Network Hardware Accelerators 665
On-FPGA real-time processing of biological signals from high-density MEAs: A design space exploration 654
Target-Aware Neural Architecture Search and Deployment for Keyword Spotting 648
Design and optimization techniques for VLSI Network on Chip architectures 609
Task-Specific Automation in Deep Learning Processes 551
Reducing False Alarms in Wearable Seizure Detection with EEGformer: A Compact Transformer Model for MCUs 504
EEGformer: Transformer-Based Epilepsy Detection on Raw EEG Traces for Low-Channel-Count Wearable Continuous Monitoring Devices 491
Real-Time sEMG Processing with Spiking Neural Networks on a Low-Power 5K-LUT FPGA 431
Optimizing Temporal Convolutional Network Inference on FPGA-Based Accelerators 346
A tiny transformer for low-power arrhythmia classification on microcontrollers 309
Design of an AI-driven Architecture with Cobots for Digital Transformation to Enhance Quality Control in the Food Industry 233
SYNtzulu: A Tiny RISC-V-Controlled SNN Processor for Real-Time Sensor Data Analysis on Low-Power FPGAs 218
null 199
On-FPGA Spiking Neural Networks for Integrated Near-Sensor ECG Analysis 156
A Runtime-Adaptive Cognitive IoT Node for Healthcare Monitoring 154
Low-Power FPGA-based Spiking Neural Networks for Real-Time Decoding of Intracortical Neural Activity 146
Wearable epilepsy seizure detection on FPGA with spiking neural networks 126
null 122
null 103
ESTU: Enabling Spiking Transformers on Ultra-Low-Power FPGAs 71
sEMG-based gesture recognition with spiking neural networks on low-power FPGA 57
Exploiting FPGAs and spiking neural networks at the micro-Edge: the EdgeAI approach 51
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs 48
Endoscopy Image Classification for Wireless Capsules with CNNs on Microcontroller-Based Platforms 44
All-Spiking ECG Analysis for Arrhythmia Classification on Low-Power FPGA 24
CNN hardware acceleration on a low-power and low-cost APSoC 2
Totale 122.726
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Categoria #
all - tutte 154.908
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 154.908
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/20213.079 0 0 0 0 0 0 0 0 0 1.166 1.156 757
2021/20225.803 742 529 197 341 502 472 217 150 462 879 719 593
2022/20239.239 609 1.155 926 944 811 1.032 508 679 616 582 941 436
2023/202410.968 568 380 496 545 1.047 1.628 1.740 696 474 831 1.488 1.075
2024/202527.861 3.278 10.616 3.119 3.074 2.788 2.477 1.299 131 207 199 412 261
2025/20266.668 485 272 741 444 529 372 2.142 353 557 773 0 0
Totale 122.726