UNICA IRIS Institutional Research Information System

MELONI, PAOLO
 Distribuzione geografica
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Continente #
EU - Europa 110.406
NA - Nord America 5.571
AS - Asia 2.014
SA - Sud America 257
AF - Africa 33
OC - Oceania 7
Continente sconosciuto - Info sul continente non disponibili 5
Totale 118.293
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Nazione #
IT - Italia 109.062
US - Stati Uniti d'America 5.466
CN - Cina 934
SG - Singapore 741
SE - Svezia 339
UA - Ucraina 332
BR - Brasile 220
DE - Germania 197
FI - Finlandia 130
GB - Regno Unito 114
VN - Vietnam 80
CA - Canada 78
FR - Francia 64
IN - India 46
KR - Corea 45
HK - Hong Kong 33
NL - Olanda 26
PL - Polonia 25
MX - Messico 22
TR - Turchia 21
ES - Italia 19
BE - Belgio 18
JP - Giappone 17
MA - Marocco 14
AR - Argentina 13
AT - Austria 11
DK - Danimarca 11
ZA - Sudafrica 11
GR - Grecia 10
BD - Bangladesh 9
IR - Iran 9
LV - Lettonia 9
RU - Federazione Russa 9
TW - Taiwan 9
LT - Lituania 8
CO - Colombia 7
KG - Kirghizistan 7
IQ - Iraq 6
SA - Arabia Saudita 6
CZ - Repubblica Ceca 5
EC - Ecuador 5
EU - Europa 5
ID - Indonesia 5
PH - Filippine 5
AE - Emirati Arabi Uniti 4
IL - Israele 4
PK - Pakistan 4
UZ - Uzbekistan 4
AU - Australia 3
AZ - Azerbaigian 3
CL - Cile 3
IE - Irlanda 3
KZ - Kazakistan 3
LK - Sri Lanka 3
LU - Lussemburgo 3
MY - Malesia 3
UY - Uruguay 3
AM - Armenia 2
CH - Svizzera 2
CY - Cipro 2
EE - Estonia 2
GE - Georgia 2
JO - Giordania 2
KE - Kenya 2
MN - Mongolia 2
NO - Norvegia 2
NZ - Nuova Zelanda 2
PE - Perù 2
PT - Portogallo 2
VE - Venezuela 2
BO - Bolivia 1
BY - Bielorussia 1
CG - Congo 1
CR - Costa Rica 1
DO - Repubblica Dominicana 1
ET - Etiopia 1
HN - Honduras 1
IS - Islanda 1
JM - Giamaica 1
LA - Repubblica Popolare Democratica del Laos 1
MG - Madagascar 1
NR - Nauru 1
OM - Oman 1
PR - Porto Rico 1
PY - Paraguay 1
SC - Seychelles 1
SK - Slovacchia (Repubblica Slovacca) 1
SN - Senegal 1
TJ - Tagikistan 1
TN - Tunisia 1
TV - Tuvalu 1
Totale 118.293
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Città #
Cagliari 105.204
Uta 3.491
Fairfield 599
Ashburn 525
Chandler 388
Singapore 371
Woodbridge 353
Dallas 330
Houston 297
Seattle 256
Wilmington 253
Nyköping 240
Boardman 229
Cambridge 229
Ann Arbor 218
Beijing 196
Jacksonville 166
Los Angeles 131
Dearborn 104
Shanghai 101
Santa Clara 94
Nanjing 85
Hefei 74
Helsinki 68
Chicago 66
Buffalo 56
Guangzhou 54
Boston 49
The Dalles 49
Ottawa 46
Seoul 41
New York 39
San Diego 37
Munich 34
Sassari 29
Frankfurt am Main 26
Redwood City 25
Hong Kong 23
Dong Ket 22
Nanchang 22
Redondo Beach 22
Rome 22
Salt Lake City 22
Warsaw 22
Washington 22
Ho Chi Minh City 21
Jiaxing 19
Milan 19
Nuremberg 19
Atlanta 18
Brussels 18
Tianjin 18
Jinan 17
London 16
Changsha 15
Council Bluffs 15
Brooklyn 14
Kunming 13
Shenyang 13
Lauterbourg 12
Toronto 12
Denver 11
Elk Grove Village 11
Hanoi 11
Mountain View 11
Tokyo 11
Brasília 10
Hangzhou 10
Montreal 10
Orange 10
Pune 10
Belo Horizonte 9
Düsseldorf 9
Mexico City 9
Phoenix 9
Riga 9
Tampa 9
Turku 9
Amsterdam 8
Casablanca 8
Copenhagen 8
Johannesburg 8
Lappeenranta 8
Rio de Janeiro 8
San Francisco 8
Shenzhen 8
São Paulo 8
Ankara 7
Bishkek 7
Hebei 7
Indiana 7
Southend 7
Taipei 7
Biên Hòa 6
Manchester 6
Ningbo 6
Poplar 6
Sterling 6
Stockholm 6
Turin 6
Totale 115.313
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Nome #
MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation 3.366
Automated Design Flow for Multi-Functional Dataflow-Based Platforms 3.131
An FPGA platform for real-time simulation of spiking neuronal networks 3.027
FPGA-Based Emulation Support for Design Space Exploration 2.836
Real-time neural signals decoding onto off-the-shelf DSP processors for neuroprosthetic applications 2.797
Neuraghe: exploiting CPU-FPGA synergies for efficient and flexible CNN inference acceleration on zynQ SoCs 2.614
Optimization and deployment of CNNs at the Edge: The ALOHA experience 2.607
Modelling and automated implementation of optimal power saving strategies in coarse-grained reconfigurable architectures 2.536
Power modelling for saving strategies in coarse grained reconfigurable systems 2.522
System adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project approach 2.515
Power and clock gating modelling in coarse grained reconfigurable systems 2.483
Exploring custom heterogeneous MPSoCs for real-time neural signal decoding 2.471
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing 2.387
Exploiting binary translation for fast ASIP design space exploration on FPGAs 2.353
ALOHA: An architectural-aware framework for deep learning at the edge 2.262
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms 2.258
Reconfigurable Coprocessors Synthesis in the MPEG-RVC Domain 2.245
Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy 2.213
ASAM: Automatic architecture synthesis and application mapping 2.190
Curbing the roofline: A scalable and flexible architecture for CNNs on FPGA 2.154
Exploiting All Programmable SoCs in Neural Signal Analysis: A Closed-Loop Control for Large-Scale CMOS Multielectrode Arrays 2.143
A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC 1.936
Runtime Energy versus Quality Tuning in Motion Compensation Filters for HEVC 1.885
A stream buffer mechanism for pervasive splitting transformations on polyhedral process networks 1.882
Online process transformation for polyhedral process networks in shared-memory MPSoCs 1.855
ALOHA: A Unified Platform-Aware Evaluation Method for CNNs Execution on Heterogeneous Systems at the Edge 1.830
A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project 1.785
SS-design: Dataflow-based design of coarse-grained: Reconfigurable platforms reconfigurable platform composer tool project - Extended abstract 1.768
Sustainable water management in quality wine-making 1.752
Architecture-aware design and implementation of CNN algorithms for embedded inference: The ALOHA project 1.672
A low overhead self-adaptation technique for KPN applications on NoC-based MPSoCs 1.661
On-the-fly adaptivity for process networks over shared-memory platforms 1.638
A runtime adaptive H.264 video-decoding MPSoC platform 1.629
Enabling fast ASIP design space exploration: An FPGA-based runtime reconfigurable prototyper 1.619
null 1.597
ASAM: Automatic Architecture Synthesis and Application Mapping 1.590
Feasibility study of real-time spiking neural network simulations on a swarm intelligence based digital architecture 1.571
Adaptivity support for MPSoCs based on process migration in polyhedral process networks 1.562
null 1.460
null 1.198
ZyON: Enabling Spike Sorting on APSoC-Based Signal Processors for High-Density Microelectrode Arrays 1.122
Routing Aware Switch Hardware Customization for Networks on Chips 1.094
Area and Power Modeling for Networks-on-Chip with Layout Awareness 1.069
Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems 1.050
A Bandwidth-Efficient Emulator of Biologically-Relevant Spiking Neural Networks on FPGA 1.048
Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper 1.032
Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures 991
Methods for hardware reduction and overall performance improvement in communication systems 977
An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures 961
Synthesis of predictable networks-on-chip-based interconnect Architectures for chip multiprocessors 959
Optimizing the serialization factor in Networks-on-Chip: a case of study 944
On the impact of serializatioin on the cache performances in Network-on-Chip based MPSoCs 884
An FPGA Research Environment for Rapid MPSoC Exploration 884
Designing Routing and Message-Dependent Deadlock Free Networks on Chips 879
Area and Power Modeling Methodologies for Networks-on-Chip 877
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs 872
Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness 855
Networks on Chips: A Synthesis Perspective 846
Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge 834
NoC Design and Implementation in 65nm Technology 829
Designing Application-Specific Networks on Chips with Floorplan Information 817
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs 808
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems-on-Chips 800
Dynamic Pruning for Parsimonious CNN Inference on Embedded Systems 794
An Adaptive Cognitive Sensor Node for ECG Monitoring in the Internet of Medical Things 742
On-FPGA Spiking Neural Networks for End-to-End Neural Decoding 730
A custom MPSoC architecture with integrated power management for real-time neural signal decoding 708
Demo: Reconfigurable Platform Composer Tool 676
Flexible acceleration of convolutions on FPGAs: Planning NEURAghe 2.0 675
Runtime adaptive iomt node on multi-core processor platform 655
Runtime-adaptive cognitive IoT nodes 632
An Adaptable Cognitive Microcontroller Node for Fitness Activity Recognition 623
Target-Aware Neural Architecture Search and Deployment for Keyword Spotting 609
An Automated Design Flow for Adaptive Neural Network Hardware Accelerators 605
On-FPGA real-time processing of biological signals from high-density MEAs: A design space exploration 600
Design and optimization techniques for VLSI Network on Chip architectures 581
Task-Specific Automation in Deep Learning Processes 516
Reducing False Alarms in Wearable Seizure Detection with EEGformer: A Compact Transformer Model for MCUs 461
EEGformer: Transformer-Based Epilepsy Detection on Raw EEG Traces for Low-Channel-Count Wearable Continuous Monitoring Devices 430
Real-Time sEMG Processing with Spiking Neural Networks on a Low-Power 5K-LUT FPGA 351
Optimizing Temporal Convolutional Network Inference on FPGA-Based Accelerators 308
A tiny transformer for low-power arrhythmia classification on microcontrollers 261
null 199
Design of an AI-driven Architecture with Cobots for Digital Transformation to Enhance Quality Control in the Food Industry 174
SYNtzulu: A Tiny RISC-V-Controlled SNN Processor for Real-Time Sensor Data Analysis on Low-Power FPGAs 156
A Runtime-Adaptive Cognitive IoT Node for Healthcare Monitoring 154
null 122
On-FPGA Spiking Neural Networks for Integrated Near-Sensor ECG Analysis 113
null 103
Low-Power FPGA-based Spiking Neural Networks for Real-Time Decoding of Intracortical Neural Activity 90
Wearable Epilepsy Seizure Detection on FPGA with Spiking Neural Networks 64
ESTU: Enabling Spiking Transformers on Ultra-Low-Power FPGAs 11
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs 10
CNN hardware acceleration on a low-power and low-cost APSoC 2
Totale 118.587
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Categoria #
all - tutte 149.084
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 149.084
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/202110.075 0 0 0 0 0 2.486 2.403 1.317 790 1.166 1.156 757
2021/20225.803 742 529 197 341 502 472 217 150 462 879 719 593
2022/20239.239 609 1.155 926 944 811 1.032 508 679 616 582 941 436
2023/202410.968 568 380 496 545 1.047 1.628 1.740 696 474 831 1.488 1.075
2024/202527.861 3.278 10.616 3.119 3.074 2.788 2.477 1.299 131 207 199 412 261
2025/20262.529 485 272 741 444 529 58 0 0 0 0 0 0
Totale 118.587