UNICA IRIS Institutional Research Information System

MELONI, PAOLO
 Distribuzione geografica
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Continente #
EU - Europa 113.309
NA - Nord America 6.774
AS - Asia 3.094
SA - Sud America 362
Continente sconosciuto - Info sul continente non disponibili 312
AF - Africa 66
OC - Oceania 9
Totale 123.926
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Nazione #
IT - Italia 111.736
US - Stati Uniti d'America 6.618
SG - Singapore 1.161
CN - Cina 1.104
SE - Svezia 376
UA - Ucraina 336
BR - Brasile 274
VN - Vietnam 240
DE - Germania 211
FI - Finlandia 168
FR - Francia 146
GB - Regno Unito 130
HK - Hong Kong 120
CA - Canada 100
IN - India 92
BD - Bangladesh 81
KR - Corea 45
NL - Olanda 34
TR - Turchia 32
PL - Polonia 27
AR - Argentina 25
JP - Giappone 25
MX - Messico 25
ES - Italia 24
IQ - Iraq 24
BE - Belgio 19
CO - Colombia 19
ZA - Sudafrica 18
PK - Pakistan 17
TW - Taiwan 16
MA - Marocco 15
SA - Arabia Saudita 14
PH - Filippine 13
AT - Austria 12
RU - Federazione Russa 12
UZ - Uzbekistan 12
VE - Venezuela 12
DK - Danimarca 11
GR - Grecia 11
CL - Cile 10
LT - Lituania 10
LV - Lettonia 10
EC - Ecuador 9
ID - Indonesia 9
IR - Iran 9
NP - Nepal 9
TN - Tunisia 9
MY - Malesia 8
KG - Kirghizistan 7
AZ - Azerbaigian 6
CZ - Repubblica Ceca 6
IE - Irlanda 6
IL - Israele 6
JM - Giamaica 6
AE - Emirati Arabi Uniti 5
AU - Australia 5
CR - Costa Rica 5
ET - Etiopia 5
EU - Europa 5
JO - Giordania 5
CH - Svizzera 4
KZ - Kazakistan 4
MN - Mongolia 4
OM - Oman 4
PE - Perù 4
PT - Portogallo 4
SN - Senegal 4
SV - El Salvador 4
BO - Bolivia 3
DO - Repubblica Dominicana 3
DZ - Algeria 3
KE - Kenya 3
LK - Sri Lanka 3
LU - Lussemburgo 3
PY - Paraguay 3
TH - Thailandia 3
UY - Uruguay 3
AM - Armenia 2
BG - Bulgaria 2
BY - Bielorussia 2
CG - Congo 2
CY - Cipro 2
EE - Estonia 2
GE - Georgia 2
GT - Guatemala 2
HN - Honduras 2
KW - Kuwait 2
NI - Nicaragua 2
NO - Norvegia 2
NZ - Nuova Zelanda 2
PS - Palestinian Territory 2
RO - Romania 2
TT - Trinidad e Tobago 2
AO - Angola 1
BB - Barbados 1
BS - Bahamas 1
IS - Islanda 1
KH - Cambogia 1
KY - Cayman, isole 1
LA - Repubblica Popolare Democratica del Laos 1
Totale 123.603
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Città #
Cagliari 107.747
Uta 3.491
Singapore 652
Ashburn 625
Fairfield 599
San Jose 425
Chandler 388
Woodbridge 354
Dallas 343
Houston 300
Seattle 256
Wilmington 254
Boardman 244
Nyköping 240
Cambridge 230
Ann Arbor 218
Beijing 214
Los Angeles 179
Jacksonville 169
Council Bluffs 151
Santa Clara 116
Helsinki 105
Shanghai 105
Dearborn 104
Hong Kong 103
Nanjing 85
Ho Chi Minh City 77
Lauterbourg 77
The Dalles 77
New York 75
Hefei 74
Chicago 69
Buffalo 60
Guangzhou 60
Boston 51
Rome 51
Hanoi 48
Ottawa 47
Milan 45
Seoul 41
San Diego 40
Munich 34
Frankfurt am Main 30
Sassari 29
Washington 26
Redwood City 25
Columbus 24
Warsaw 23
Dong Ket 22
Nanchang 22
Redondo Beach 22
Salt Lake City 22
Atlanta 21
Tianjin 21
Nuremberg 20
Jiaxing 19
London 19
Orem 19
Brooklyn 18
Brussels 18
Denver 18
Jinan 18
Toronto 18
Tokyo 16
Changsha 15
Chennai 15
Montreal 14
Phoenix 14
Shenyang 14
São Paulo 14
Kunming 13
Pune 13
Taipei 13
Amsterdam 12
Brasília 12
Hangzhou 12
San Francisco 12
Baghdad 11
Elk Grove Village 11
Johannesburg 11
Mountain View 11
Shenzhen 11
Belo Horizonte 10
Orange 10
Riga 10
Tampa 10
Düsseldorf 9
Haiphong 9
Lappeenranta 9
Mexico City 9
Tashkent 9
Turku 9
Casablanca 8
Copenhagen 8
Da Nang 8
Istanbul 8
Manchester 8
Mumbai 8
Naples 8
Rio de Janeiro 8
Totale 119.479
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Nome #
MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation 3.414
Automated Design Flow for Multi-Functional Dataflow-Based Platforms 3.176
An FPGA platform for real-time simulation of spiking neuronal networks 3.080
FPGA-Based Emulation Support for Design Space Exploration 2.878
Real-time neural signals decoding onto off-the-shelf DSP processors for neuroprosthetic applications 2.854
Optimization and deployment of CNNs at the Edge: The ALOHA experience 2.664
Neuraghe: exploiting CPU-FPGA synergies for efficient and flexible CNN inference acceleration on zynQ SoCs 2.662
Modelling and automated implementation of optimal power saving strategies in coarse-grained reconfigurable architectures 2.613
Power modelling for saving strategies in coarse grained reconfigurable systems 2.588
System adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project approach 2.567
Power and clock gating modelling in coarse grained reconfigurable systems 2.540
Exploring custom heterogeneous MPSoCs for real-time neural signal decoding 2.527
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing 2.476
Exploiting binary translation for fast ASIP design space exploration on FPGAs 2.400
ALOHA: An architectural-aware framework for deep learning at the edge 2.319
Reconfigurable Coprocessors Synthesis in the MPEG-RVC Domain 2.310
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms 2.296
Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy 2.266
ASAM: Automatic architecture synthesis and application mapping 2.249
Exploiting All Programmable SoCs in Neural Signal Analysis: A Closed-Loop Control for Large-Scale CMOS Multielectrode Arrays 2.212
Curbing the roofline: A scalable and flexible architecture for CNNs on FPGA 2.211
A stream buffer mechanism for pervasive splitting transformations on polyhedral process networks 2.009
A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC 1.979
Runtime Energy versus Quality Tuning in Motion Compensation Filters for HEVC 1.935
Online process transformation for polyhedral process networks in shared-memory MPSoCs 1.901
ALOHA: A Unified Platform-Aware Evaluation Method for CNNs Execution on Heterogeneous Systems at the Edge 1.894
A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project 1.843
Sustainable water management in quality wine-making 1.838
SS-design: Dataflow-based design of coarse-grained: Reconfigurable platforms reconfigurable platform composer tool project - Extended abstract 1.825
Architecture-aware design and implementation of CNN algorithms for embedded inference: The ALOHA project 1.732
A low overhead self-adaptation technique for KPN applications on NoC-based MPSoCs 1.720
On-the-fly adaptivity for process networks over shared-memory platforms 1.705
A runtime adaptive H.264 video-decoding MPSoC platform 1.675
Enabling fast ASIP design space exploration: An FPGA-based runtime reconfigurable prototyper 1.661
ASAM: Automatic Architecture Synthesis and Application Mapping 1.640
Adaptivity support for MPSoCs based on process migration in polyhedral process networks 1.624
null 1.597
Feasibility study of real-time spiking neural network simulations on a swarm intelligence based digital architecture 1.571
null 1.460
null 1.198
ZyON: Enabling Spike Sorting on APSoC-Based Signal Processors for High-Density Microelectrode Arrays 1.178
Routing Aware Switch Hardware Customization for Networks on Chips 1.137
Area and Power Modeling for Networks-on-Chip with Layout Awareness 1.129
A Bandwidth-Efficient Emulator of Biologically-Relevant Spiking Neural Networks on FPGA 1.117
Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems 1.093
Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper 1.063
Methods for hardware reduction and overall performance improvement in communication systems 1.049
Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures 1.034
An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures 1.008
Synthesis of predictable networks-on-chip-based interconnect Architectures for chip multiprocessors 1.000
Optimizing the serialization factor in Networks-on-Chip: a case of study 995
Area and Power Modeling Methodologies for Networks-on-Chip 931
An FPGA Research Environment for Rapid MPSoC Exploration 922
On the impact of serializatioin on the cache performances in Network-on-Chip based MPSoCs 920
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs 920
Designing Routing and Message-Dependent Deadlock Free Networks on Chips 916
Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness 910
Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge 888
Networks on Chips: A Synthesis Perspective 887
NoC Design and Implementation in 65nm Technology 872
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs 862
Dynamic Pruning for Parsimonious CNN Inference on Embedded Systems 856
Designing Application-Specific Networks on Chips with Floorplan Information 855
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems-on-Chips 841
On-FPGA Spiking Neural Networks for End-to-End Neural Decoding 818
An Adaptive Cognitive Sensor Node for ECG Monitoring in the Internet of Medical Things 806
A custom MPSoC architecture with integrated power management for real-time neural signal decoding 764
Flexible acceleration of convolutions on FPGAs: Planning NEURAghe 2.0 740
Demo: Reconfigurable Platform Composer Tool 726
Runtime adaptive iomt node on multi-core processor platform 718
An Adaptable Cognitive Microcontroller Node for Fitness Activity Recognition 709
Runtime-adaptive cognitive IoT nodes 692
An Automated Design Flow for Adaptive Neural Network Hardware Accelerators 683
Target-Aware Neural Architecture Search and Deployment for Keyword Spotting 668
On-FPGA real-time processing of biological signals from high-density MEAs: A design space exploration 662
Design and optimization techniques for VLSI Network on Chip architectures 615
Task-Specific Automation in Deep Learning Processes 563
Reducing False Alarms in Wearable Seizure Detection with EEGformer: A Compact Transformer Model for MCUs 520
EEGformer: Transformer-Based Epilepsy Detection on Raw EEG Traces for Low-Channel-Count Wearable Continuous Monitoring Devices 510
Real-Time sEMG Processing with Spiking Neural Networks on a Low-Power 5K-LUT FPGA 470
Optimizing Temporal Convolutional Network Inference on FPGA-Based Accelerators 356
A tiny transformer for low-power arrhythmia classification on microcontrollers 327
Design of an AI-driven Architecture with Cobots for Digital Transformation to Enhance Quality Control in the Food Industry 251
SYNtzulu: A Tiny RISC-V-Controlled SNN Processor for Real-Time Sensor Data Analysis on Low-Power FPGAs 233
null 199
Low-Power FPGA-based Spiking Neural Networks for Real-Time Decoding of Intracortical Neural Activity 172
On-FPGA Spiking Neural Networks for Integrated Near-Sensor ECG Analysis 169
Wearable epilepsy seizure detection on FPGA with spiking neural networks 162
A Runtime-Adaptive Cognitive IoT Node for Healthcare Monitoring 154
ESTU: Enabling Spiking Transformers on Ultra-Low-Power FPGAs 129
null 122
sEMG-based gesture recognition with spiking neural networks on low-power FPGA 105
null 103
All-Spiking ECG Analysis for Arrhythmia Classification on Low-Power FPGA 94
Exploiting FPGAs and spiking neural networks at the micro-Edge: the EdgeAI approach 79
Endoscopy Image Classification for Wireless Capsules with CNNs on Microcontroller-Based Platforms 57
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs 56
CNN hardware acceleration on a low-power and low-cost APSoC 2
Totale 123.926
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Categoria #
all - tutte 160.383
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 160.383
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/20225.061 0 529 197 341 502 472 217 150 462 879 719 593
2022/20239.239 609 1.155 926 944 811 1.032 508 679 616 582 941 436
2023/202410.968 568 380 496 545 1.047 1.628 1.740 696 474 831 1.488 1.075
2024/202527.861 3.278 10.616 3.119 3.074 2.788 2.477 1.299 131 207 199 412 261
2025/20267.440 485 272 741 444 529 372 2.142 353 557 786 510 249
2026/2027428 178 250 0 0 0 0 0 0 0 0 0 0
Totale 123.926