UNICA IRIS Institutional Research Information System

PALUMBO, FRANCESCA
 Distribuzione geografica
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Continente #
EU - Europa 99.761
NA - Nord America 5.166
AS - Asia 2.471
SA - Sud America 310
AF - Africa 71
OC - Oceania 9
Continente sconosciuto - Info sul continente non disponibili 2
Totale 107.790
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Nazione #
IT - Italia 98.608
US - Stati Uniti d'America 5.093
SG - Singapore 988
CN - Cina 925
UA - Ucraina 272
BR - Brasile 233
SE - Svezia 228
VN - Vietnam 209
DE - Germania 140
FI - Finlandia 138
FR - Francia 114
GB - Regno Unito 93
HK - Hong Kong 68
IN - India 67
CA - Canada 43
MA - Marocco 38
NL - Olanda 36
AR - Argentina 28
BD - Bangladesh 26
KR - Corea 25
TR - Turchia 23
MX - Messico 22
ES - Italia 20
PL - Polonia 20
IE - Irlanda 17
IQ - Iraq 17
JP - Giappone 17
AT - Austria 16
BE - Belgio 15
RU - Federazione Russa 14
CO - Colombia 12
PH - Filippine 12
PK - Pakistan 12
EC - Ecuador 11
IL - Israele 8
SA - Arabia Saudita 8
LT - Lituania 7
UZ - Uzbekistan 7
ZA - Sudafrica 7
CL - Cile 6
ID - Indonesia 6
IR - Iran 6
JO - Giordania 6
VE - Venezuela 6
AU - Australia 5
AZ - Azerbaigian 5
CZ - Repubblica Ceca 5
KE - Kenya 5
MY - Malesia 5
PE - Perù 5
TN - Tunisia 5
BO - Bolivia 4
EG - Egitto 4
AE - Emirati Arabi Uniti 3
BY - Bielorussia 3
NP - Nepal 3
NZ - Nuova Zelanda 3
PS - Palestinian Territory 3
TW - Taiwan 3
AL - Albania 2
BG - Bulgaria 2
DK - Danimarca 2
DZ - Algeria 2
ET - Etiopia 2
EU - Europa 2
HR - Croazia 2
KG - Kirghizistan 2
KZ - Kazakistan 2
LV - Lettonia 2
PR - Porto Rico 2
PY - Paraguay 2
QA - Qatar 2
TH - Thailandia 2
UY - Uruguay 2
AM - Armenia 1
BF - Burkina Faso 1
BH - Bahrain 1
CG - Congo 1
CH - Svizzera 1
CI - Costa d'Avorio 1
CR - Costa Rica 1
CY - Cipro 1
DO - Repubblica Dominicana 1
GE - Georgia 1
GR - Grecia 1
HN - Honduras 1
IM - Isola di Man 1
JM - Giamaica 1
KW - Kuwait 1
LA - Repubblica Popolare Democratica del Laos 1
LB - Libano 1
LK - Sri Lanka 1
LY - Libia 1
MG - Madagascar 1
MN - Mongolia 1
MU - Mauritius 1
NI - Nicaragua 1
NO - Norvegia 1
OM - Oman 1
PA - Panama 1
Totale 107.784
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Città #
Cagliari 95.740
Uta 2.562
Ashburn 535
Singapore 526
Fairfield 472
Woodbridge 385
San Jose 315
Chandler 296
Dallas 282
Houston 271
Boardman 215
Wilmington 206
Seattle 197
Ann Arbor 196
Cambridge 187
Beijing 174
Nyköping 157
Jacksonville 137
Los Angeles 130
Dearborn 119
Santa Clara 92
Helsinki 87
Shanghai 87
Nanjing 69
Lauterbourg 66
Ho Chi Minh City 65
Hong Kong 64
Hefei 45
Buffalo 44
Boston 41
Council Bluffs 39
Rome 37
Dong Ket 32
Hanoi 32
Casablanca 30
San Diego 30
The Dalles 29
Redwood City 27
Guangzhou 26
New York 26
Atlanta 25
Amsterdam 24
Seoul 22
Chicago 21
São Paulo 20
Tianjin 19
Nanchang 18
Nuremberg 18
Orem 18
Changsha 17
Dublin 17
Milan 17
Sassari 17
Brooklyn 16
Warsaw 16
Brussels 15
Frankfurt am Main 15
Jiaxing 15
Mountain View 15
Chennai 14
Munich 14
Hangzhou 13
Kunming 13
Montreal 13
Tokyo 13
Denver 12
La Maddalena 12
Shenyang 12
Turin 12
Jinan 11
Lappeenranta 11
London 11
Ottawa 11
Phoenix 11
Redondo Beach 11
Toronto 11
Washington 11
Düsseldorf 10
Mumbai 10
Hebei 9
Orange 9
Vienna 9
Haiphong 8
Norwalk 8
Shenzhen 8
Elk Grove Village 7
Madrid 7
Mexico City 7
Tashkent 7
Xi'an 7
Alghero 6
Amman 6
Auburn Hills 6
Brasília 6
Da Nang 6
Decimomannu 6
Lahore 6
Poplar 6
Quartu Sant'Elena 6
Quito 6
Totale 104.797
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Nome #
MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation 3.400
Automated Design Flow for Multi-Functional Dataflow-Based Platforms 3.169
An FPGA platform for real-time simulation of spiking neuronal networks 3.060
Adaptable AES implementation with power-gating support 2.950
Neu Pow: Artificial Neural Networks for Power and Behavioral Modeling of Arithmetic Components in 45nm ASICs Technology 2.685
Optimization and deployment of CNNs at the Edge: The ALOHA experience 2.651
Modelling and automated implementation of optimal power saving strategies in coarse-grained reconfigurable architectures 2.603
Power modelling for saving strategies in coarse grained reconfigurable systems 2.577
null 2.541
Power and clock gating modelling in coarse grained reconfigurable systems 2.526
Exploring custom heterogeneous MPSoCs for real-time neural signal decoding 2.523
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing 2.455
Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy 2.400
An integrated hardware/software design methodology for signal processing systems 2.329
ALOHA: An architectural-aware framework for deep learning at the edge 2.308
Reconfigurable Coprocessors Synthesis in the MPEG-RVC Domain 2.297
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms 2.290
Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy 2.252
Profiling of Dataflow-Based Coarse-Grained Reconfigurable Platforms 2.080
Automated power gating methodology for dataflow-based reconfigurable systems 2.070
Computing swarms for self-adaptiveness and self-organizationin floating-point array processing 2.026
Runtime Energy versus Quality Tuning in Motion Compensation Filters for HEVC 1.930
Coarse-grained reconfiguration: dataflow-based power management 1.906
Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems 1.874
Hardware design methodology using lightweight dataflow and its integration with low power techniques 1.842
SS-design: Dataflow-based design of coarse-grained: Reconfigurable platforms reconfigurable platform composer tool project - Extended abstract 1.817
A nature-inspired adaptive floating-point coprocessing system 1.756
Dataflow-functional high-level synthesis for coarse-grained reconfigurable accelerators 1.754
Architecture-aware design and implementation of CNN algorithms for embedded inference: The ALOHA project 1.719
null 1.697
On-the-fly adaptivity for process networks over shared-memory platforms 1.696
A coarse-grained reconfigurable approach for low-power spike sorting architectures 1.687
Automatic Generation of Dataflow-Based Reconfigurable Co-processing Units 1.590
Feasibility study of real-time spiking neural network simulations on a swarm intelligence based digital architecture 1.571
Concurrent hybrid switching for massively parallel systems-on-chip: The CYBER architecture 1.462
null 1.423
Challenging CPS trade-off adaptivity with coarse-grained reconfiguration 1.266
CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of Reconfigurable systems in unceRtain hybRid envirOnments 1.221
A fast MPI-based parallel framework for cycle-accurate HDL multi-parametric simulations 1.166
Low power design methodology for signal processing systems using lightweight dataflow techniques 1.138
NeuPow: A CAD Methodology for High-level Power Estimation Based on Machine Learning 1.121
Feasibility study and porting of the damped least square algorithm on FPGA 1.070
Impact of half-duplex and full-duplex DMA Implementations on NoC performance 1.041
Design IP Faster: Introducing the C~ High-Level Language 961
Towards self-adaptive networks on chip for massively parallel processors: Multilevel quality of service programmability 959
The multi-dataflow composer tool: A runtime reconfigurable HDL platform composer 935
A coarse-grained reconfigurable wavelet denoiser exploiting the multi-dataflow composer tool 893
null 876
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs 854
null 831
null 822
Reconfigurable Adaptive Multiple Transform Hardware Solutions for Versatile Video Coding 817
RVC: A multi-decoder CAL Composer tool 795
sysCgrid – SystemC grid simulation framework 782
Non-Exclusive Dual-Mode Approach for NoC Designs 777
Coarse-Grained Reconfigurable Approach for Multi-Dataflow Systems 721
Demo: Reconfigurable Platform Composer Tool 720
A multithread AES accelerator for Cyber-Physical Systems 680
An Automated Design Flow for Adaptive Neural Network Hardware Accelerators 665
The FitOptiVis ECSEL Project: Highly Efficient Distributed Embedded Image/Video Processing in Cyber-Physical Systems Invited Paper 661
The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design 634
Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project 591
Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAPI 574
Multithread Accelerators on FPGAs: A Dataflow-Based Approach 513
A surface tension and coalescence model for dynamic distributed resources allocation in Massively Parallel Processors on-Chip 375
A Composable Monitoring System for Heterogeneous Embedded Platforms 363
Hybrid switching techniques for heterogeneous traffic support in multi-processors system on chip and massively parallel processors 353
A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching 350
A Novel Non-Exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs 349
Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project 266
PathTracer: Understanding Response Time of Signal Processing Applications on Heterogeneous MPSoCs 233
In-field automatic detection of grape bunches under a totally uncontrolled environment 218
Unmanned vehicles in smart farming: A survey and a glance at future horizons 215
A Dataflow Implementation of Inverse Kinematics on Reconfigurable Heterogeneous MPSoC 214
MYRTUS: Multi-layer 360° dYnamic orchestration and interopeRable design environmenT for compute-continUum Systems 213
PathTracing: Raising the level of understanding of processing latency in heterogeneous MPSoCs 207
Elicitation of technical requirements in large research projects: The CERBERO approach 182
Reconfigurable and approximate computing for video coding 168
Adaptive software-augmented hardware reconfiguration with dataflow design automation 167
Message from the Program Chairs 147
Dataflow modeling for reconfigurable signal processing systems 136
Cross-layer design of reconfigurable cyber-physical systems 133
Exploring the performance of partially reconfigurable point-to-point interconnects 126
Runtime reconfigurable FPGA accelerator for tactile texture classification based shallow CNN 80
Multi-Partner Project: Key Enabling Technologies for Cognitive Computing Continuum - MYRTUS Project Perspective 80
FPGA-based Implementation for Industrial Motion Control System 73
An FPGA-based accelerator design methodology for smart UAVs in precision agriculture: A case study 70
Integrating FPGA-Based Acceleration in Industrial Motion Control System 65
Adaptive CNN acceleration on FPGAs: closing the gap with state-of-the-art solutions 63
SECURED for health: Scaling up privacy to enable the integration of the european health data space 62
ONNX-To-Hardware Design Flow for Adaptive Neural-Network Inference on FPGAs 50
Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design 49
Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach 48
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs 46
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case 40
DSE and profiling of multi-context coarse-grained reconfigurable systems 32
Multi-purpose systems: A novel dataflow-based generation and mapping strategy 26
Totale 108.199
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Categoria #
all - tutte 133.184
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 133.184
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/20212.849 0 0 0 0 0 0 0 0 0 975 1.198 676
2021/20225.457 627 496 257 323 429 522 194 151 439 671 755 593
2022/20236.458 399 719 565 619 522 720 394 577 440 462 644 397
2023/20248.159 481 285 334 393 680 1.350 843 616 322 579 1.179 1.097
2024/202523.529 4.093 7.993 2.449 2.457 2.557 1.831 1.492 69 133 122 139 194
2025/20265.729 354 204 540 509 625 425 1.142 641 415 874 0 0
Totale 108.199