UNICA IRIS Institutional Research Information System

PALUMBO, FRANCESCA
 Distribuzione geografica
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Continente #
EU - Europa 98.035
NA - Nord America 4.620
AS - Asia 1.747
SA - Sud America 241
AF - Africa 48
OC - Oceania 9
Continente sconosciuto - Info sul continente non disponibili 2
Totale 104.702
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Nazione #
IT - Italia 97.036
US - Stati Uniti d'America 4.560
SG - Singapore 731
CN - Cina 729
UA - Ucraina 270
SE - Svezia 228
BR - Brasile 202
DE - Germania 130
VN - Vietnam 111
FI - Finlandia 91
GB - Regno Unito 83
FR - Francia 47
CA - Canada 40
MA - Marocco 36
NL - Olanda 30
IN - India 27
KR - Corea 25
HK - Hong Kong 20
PL - Polonia 19
ES - Italia 18
TR - Turchia 18
MX - Messico 17
AR - Argentina 16
AT - Austria 16
BE - Belgio 15
IE - Irlanda 15
JP - Giappone 13
BD - Bangladesh 12
RU - Federazione Russa 12
CO - Colombia 8
IQ - Iraq 8
IL - Israele 7
IR - Iran 6
SA - Arabia Saudita 6
AU - Australia 5
CZ - Repubblica Ceca 5
LT - Lituania 5
UZ - Uzbekistan 5
ZA - Sudafrica 5
EC - Ecuador 4
BY - Bielorussia 3
CL - Cile 3
ID - Indonesia 3
JO - Giordania 3
NZ - Nuova Zelanda 3
PH - Filippine 3
PK - Pakistan 3
AL - Albania 2
AZ - Azerbaigian 2
BO - Bolivia 2
DK - Danimarca 2
EU - Europa 2
HR - Croazia 2
KE - Kenya 2
KG - Kirghizistan 2
LV - Lettonia 2
PE - Perù 2
TW - Taiwan 2
UY - Uruguay 2
VE - Venezuela 2
AE - Emirati Arabi Uniti 1
AM - Armenia 1
BG - Bulgaria 1
BH - Bahrain 1
CG - Congo 1
CI - Costa d'Avorio 1
CY - Cipro 1
DO - Repubblica Dominicana 1
EG - Egitto 1
GE - Georgia 1
GR - Grecia 1
IM - Isola di Man 1
JM - Giamaica 1
KZ - Kazakistan 1
LA - Repubblica Popolare Democratica del Laos 1
LK - Sri Lanka 1
MG - Madagascar 1
MY - Malesia 1
NO - Norvegia 1
OM - Oman 1
PR - Porto Rico 1
PS - Palestinian Territory 1
TV - Tuvalu 1
ZW - Zimbabwe 1
Totale 104.702
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Città #
Cagliari 94.183
Uta 2.562
Fairfield 472
Ashburn 448
Woodbridge 385
Singapore 326
Chandler 296
Dallas 280
Houston 271
Boardman 215
Wilmington 205
Seattle 197
Ann Arbor 196
Cambridge 187
Beijing 162
Nyköping 157
Jacksonville 136
Dearborn 119
Los Angeles 104
Santa Clara 86
Shanghai 83
Nanjing 69
Helsinki 47
Hefei 45
Buffalo 43
Boston 41
Rome 34
Ho Chi Minh City 33
Dong Ket 32
Casablanca 30
San Diego 30
Redwood City 27
Atlanta 22
New York 22
Seoul 22
Amsterdam 20
Guangzhou 20
Hong Kong 18
Nanchang 18
Chicago 17
Council Bluffs 17
Milan 17
Sassari 17
Tianjin 17
Brooklyn 16
Nuremberg 16
São Paulo 16
Brussels 15
Changsha 15
Dublin 15
Jiaxing 15
Mountain View 15
Warsaw 15
Munich 14
The Dalles 14
Kunming 13
Denver 12
Hangzhou 12
Hanoi 12
La Maddalena 12
Tokyo 12
Turin 12
Jinan 11
London 11
Ottawa 11
Redondo Beach 11
Shenyang 11
Toronto 11
Washington 11
Düsseldorf 10
Montreal 10
Phoenix 10
Frankfurt am Main 9
Hebei 9
Orange 9
Vienna 9
Norwalk 8
Elk Grove Village 7
Alghero 6
Auburn Hills 6
Decimomannu 6
Lauterbourg 6
Madrid 6
Mexico City 6
Poplar 6
Quartu Sant'Elena 6
Salt Lake City 6
Xi'an 6
Azor 5
Brasília 5
Columbus 5
Fuzhou 5
Mumbai 5
Rio de Janeiro 5
San Francisco 5
Stockholm 5
Tashkent 5
Ankara 4
Belo Horizonte 4
Chennai 4
Totale 102.254
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Nome #
MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation 3.369
Automated Design Flow for Multi-Functional Dataflow-Based Platforms 3.136
An FPGA platform for real-time simulation of spiking neuronal networks 3.031
Adaptable AES implementation with power-gating support 2.915
Neu Pow: Artificial Neural Networks for Power and Behavioral Modeling of Arithmetic Components in 45nm ASICs Technology 2.645
Optimization and deployment of CNNs at the Edge: The ALOHA experience 2.610
null 2.541
Modelling and automated implementation of optimal power saving strategies in coarse-grained reconfigurable architectures 2.540
Power modelling for saving strategies in coarse grained reconfigurable systems 2.527
Power and clock gating modelling in coarse grained reconfigurable systems 2.487
Exploring custom heterogeneous MPSoCs for real-time neural signal decoding 2.476
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing 2.394
Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy 2.377
An integrated hardware/software design methodology for signal processing systems 2.296
ALOHA: An architectural-aware framework for deep learning at the edge 2.266
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms 2.259
Reconfigurable Coprocessors Synthesis in the MPEG-RVC Domain 2.248
Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy 2.214
Profiling of Dataflow-Based Coarse-Grained Reconfigurable Platforms 2.052
Automated power gating methodology for dataflow-based reconfigurable systems 2.030
Computing swarms for self-adaptiveness and self-organizationin floating-point array processing 1.991
Runtime Energy versus Quality Tuning in Motion Compensation Filters for HEVC 1.888
Coarse-grained reconfiguration: dataflow-based power management 1.864
Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems 1.845
Hardware design methodology using lightweight dataflow and its integration with low power techniques 1.807
SS-design: Dataflow-based design of coarse-grained: Reconfigurable platforms reconfigurable platform composer tool project - Extended abstract 1.770
A nature-inspired adaptive floating-point coprocessing system 1.723
Dataflow-functional high-level synthesis for coarse-grained reconfigurable accelerators 1.721
null 1.697
Architecture-aware design and implementation of CNN algorithms for embedded inference: The ALOHA project 1.677
A coarse-grained reconfigurable approach for low-power spike sorting architectures 1.662
On-the-fly adaptivity for process networks over shared-memory platforms 1.641
Feasibility study of real-time spiking neural network simulations on a swarm intelligence based digital architecture 1.571
Automatic Generation of Dataflow-Based Reconfigurable Co-processing Units 1.547
Concurrent hybrid switching for massively parallel systems-on-chip: The CYBER architecture 1.438
null 1.423
Challenging CPS trade-off adaptivity with coarse-grained reconfiguration 1.266
CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of Reconfigurable systems in unceRtain hybRid envirOnments 1.221
A fast MPI-based parallel framework for cycle-accurate HDL multi-parametric simulations 1.143
Low power design methodology for signal processing systems using lightweight dataflow techniques 1.138
NeuPow: A CAD Methodology for High-level Power Estimation Based on Machine Learning 1.083
Feasibility study and porting of the damped least square algorithm on FPGA 1.032
Impact of half-duplex and full-duplex DMA Implementations on NoC performance 1.022
Design IP Faster: Introducing the C~ High-Level Language 935
Towards self-adaptive networks on chip for massively parallel processors: Multilevel quality of service programmability 930
The multi-dataflow composer tool: A runtime reconfigurable HDL platform composer 911
null 876
A coarse-grained reconfigurable wavelet denoiser exploiting the multi-dataflow composer tool 856
null 831
null 822
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs 812
Reconfigurable Adaptive Multiple Transform Hardware Solutions for Versatile Video Coding 787
RVC: A multi-decoder CAL Composer tool 773
Non-Exclusive Dual-Mode Approach for NoC Designs 764
sysCgrid – SystemC grid simulation framework 762
Coarse-Grained Reconfigurable Approach for Multi-Dataflow Systems 691
Demo: Reconfigurable Platform Composer Tool 678
The FitOptiVis ECSEL Project: Highly Efficient Distributed Embedded Image/Video Processing in Cyber-Physical Systems Invited Paper 661
A multithread AES accelerator for Cyber-Physical Systems 636
An Automated Design Flow for Adaptive Neural Network Hardware Accelerators 610
The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design 597
Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project 558
Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAPI 537
Multithread Accelerators on FPGAs: A Dataflow-Based Approach 472
A surface tension and coalescence model for dynamic distributed resources allocation in Massively Parallel Processors on-Chip 352
A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching 333
Hybrid switching techniques for heterogeneous traffic support in multi-processors system on chip and massively parallel processors 327
A Novel Non-Exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs 325
A Composable Monitoring System for Heterogeneous Embedded Platforms 309
Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project 214
PathTracer: Understanding Response Time of Signal Processing Applications on Heterogeneous MPSoCs 181
In-field automatic detection of grape bunches under a totally uncontrolled environment 175
A Dataflow Implementation of Inverse Kinematics on Reconfigurable Heterogeneous MPSoC 172
PathTracing: Raising the level of understanding of processing latency in heterogeneous MPSoCs 172
Unmanned vehicles in smart farming: A survey and a glance at future horizons 171
Elicitation of technical requirements in large research projects: The CERBERO approach 154
Reconfigurable and approximate computing for video coding 145
Adaptive software-augmented hardware reconfiguration with dataflow design automation 140
MYRTUS: Multi-layer 360° dYnamic orchestration and interopeRable design environmenT for compute-continUum Systems 136
Message from the Program Chairs 132
Dataflow modeling for reconfigurable signal processing systems 121
Exploring the performance of partially reconfigurable point-to-point interconnects 116
Cross-layer design of reconfigurable cyber-physical systems 111
Multi-Partner Project: Key Enabling Technologies for Cognitive Computing Continuum - MYRTUS Project Perspective 47
FPGA-based Implementation for Industrial Motion Control System 39
SECURED for health: Scaling up privacy to enable the integration of the european health data space 28
Integrating FPGA-Based Acceleration in Industrial Motion Control System 24
ONNX-To-Hardware Design Flow for Adaptive Neural-Network Inference on FPGAs 19
Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach 15
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs 14
Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design 14
An FPGA-based accelerator design methodology for smart UAVs in precision agriculture: A case study 14
Multi-purpose systems: A novel dataflow-based generation and mapping strategy 9
DSE and profiling of multi-context coarse-grained reconfigurable systems 6
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case 4
Totale 105.101
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Categoria #
all - tutte 129.124
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 129.124
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/20218.916 0 0 0 0 0 2.180 2.017 1.253 617 975 1.198 676
2021/20225.457 627 496 257 323 429 522 194 151 439 671 755 593
2022/20236.458 399 719 565 619 522 720 394 577 440 462 644 397
2023/20248.159 481 285 334 393 680 1.350 843 616 322 579 1.179 1.097
2024/202523.529 4.093 7.993 2.449 2.457 2.557 1.831 1.492 69 133 122 139 194
2025/20262.631 354 204 540 509 625 399 0 0 0 0 0 0
Totale 105.101