UNICA IRIS Institutional Research Information System

PALUMBO, FRANCESCA
 Distribuzione geografica
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Continente #
EU - Europa 67.343
NA - Nord America 3.052
AS - Asia 355
Continente sconosciuto - Info sul continente non disponibili 2
OC - Oceania 2
SA - Sud America 1
Totale 70.755
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Nazione #
IT - Italia 66.679
US - Stati Uniti d'America 3.038
CN - Cina 264
UA - Ucraina 225
SE - Svezia 215
FI - Finlandia 67
DE - Germania 59
GB - Regno Unito 48
SG - Singapore 35
VN - Vietnam 28
FR - Francia 20
CA - Canada 14
BE - Belgio 13
RU - Federazione Russa 7
IN - India 6
IL - Israele 5
IR - Iran 5
ES - Italia 4
KR - Corea 3
TR - Turchia 3
CZ - Repubblica Ceca 2
EU - Europa 2
JP - Giappone 2
NL - Olanda 2
NZ - Nuova Zelanda 2
BR - Brasile 1
CY - Cipro 1
GR - Grecia 1
LK - Sri Lanka 1
MY - Malesia 1
NO - Norvegia 1
TW - Taiwan 1
Totale 70.755
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Città #
Cagliari 66.513
Fairfield 434
Woodbridge 321
Chandler 308
Houston 246
Ashburn 245
Seattle 180
Ann Arbor 176
Wilmington 175
Nyköping 162
Cambridge 161
Jacksonville 113
Dearborn 110
Nanjing 57
Boardman 54
Beijing 47
Helsinki 37
Boston 33
Dong Ket 28
Shanghai 27
San Diego 26
Redwood City 24
Los Angeles 20
Nanchang 17
Sassari 16
Mountain View 14
Brussels 13
Changsha 13
Guangzhou 13
Kunming 10
Jiaxing 9
Jinan 9
New York 9
Orange 9
Shenyang 9
Toronto 9
Atlanta 8
Hebei 8
Tianjin 8
Washington 8
Hangzhou 7
Hefei 7
Milan 6
Norwalk 6
Azor 5
London 5
Auburn Hills 4
Fuzhou 4
Madrid 4
Phoenix 4
Quartu Sant'Elena 4
Stuttgart 4
Alghero 3
Brescia 3
Gonnosfanàdiga 3
Indiana 3
Ningbo 3
Ottawa 3
Torino 3
Baotou 2
Borås 2
Edinburgh 2
Hillsboro 2
Maracalagonis 2
Millbury 2
Pinehaven 2
Porto Torres 2
Pune 2
Quartu Sant'elena 2
Redmond 2
Rome 2
Selargius 2
Shaoxing 2
Shenzhen 2
Tappahannock 2
Walnut 2
Yellow Springs 2
Baricella 1
Biassono 1
Billings 1
Brno 1
Cedar Knolls 1
Centro 1
Changchun 1
Chaoyang 1
Chelyabinsk 1
Chicago 1
Colombo 1
Decimomannu 1
Denver 1
El Cajon 1
Falkenstein 1
Fars 1
Fremont 1
Halifax 1
Hounslow 1
Izhevsk 1
Izmir 1
Kilburn 1
Kuala Lumpur 1
Totale 69.819
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Nome #
Automated Design Flow for Multi-Functional Dataflow-Based Platforms 2.594
An FPGA platform for real-time simulation of spiking neuronal networks 2.296
Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design 2.280
Power modelling for saving strategies in coarse grained reconfigurable systems 2.191
Modelling and automated implementation of optimal power saving strategies in coarse-grained reconfigurable architectures 2.163
Power and clock gating modelling in coarse grained reconfigurable systems 2.140
Exploring custom heterogeneous MPSoCs for real-time neural signal decoding 2.118
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing 1.979
ALOHA: An architectural-aware framework for deep learning at the edge 1.975
Reconfigurable Coprocessors Synthesis in the MPEG-RVC Domain 1.936
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms 1.927
Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy 1.839
Adaptable AES implementation with power-gating support 1.800
An integrated hardware/software design methodology for signal processing systems 1.796
Automated power gating methodology for dataflow-based reconfigurable systems 1.743
Feasibility study of real-time spiking neural network simulations on a swarm intelligence based digital architecture 1.571
Coarse-grained reconfiguration: dataflow-based power management 1.537
null 1.529
Runtime Energy versus Quality Tuning in Motion Compensation Filters for HEVC 1.523
null 1.401
Optimization and deployment of CNNs at the Edge: The ALOHA experience 1.393
Architecture-aware design and implementation of CNN algorithms for embedded inference: The ALOHA project 1.377
Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy 1.368
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case 1.348
null 1.339
Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems 1.336
null 1.329
A nature-inspired adaptive floating-point coprocessing system 1.316
Concurrent hybrid switching for massively parallel systems-on-chip: The CYBER architecture 1.282
Challenging CPS trade-off adaptivity with coarse-grained reconfiguration 1.265
null 1.220
Automatic Generation of Dataflow-Based Reconfigurable Co-processing Units 1.194
A coarse-grained reconfigurable approach for low-power spike sorting architectures 1.170
DSE and profiling of multi-context coarse-grained reconfigurable systems 1.139
null 1.137
A fast MPI-based parallel framework for cycle-accurate HDL multi-parametric simulations 926
Impact of half-duplex and full-duplex DMA Implementations on NoC performance 834
null 821
Towards self-adaptive networks on chip for massively parallel processors: Multilevel quality of service programmability 787
Design IP Faster: Introducing the C~ High-Level Language 760
Multi-purpose systems: A novel dataflow-based generation and mapping strategy 745
The multi-dataflow composer tool: A runtime reconfigurable HDL platform composer 737
Non-Exclusive Dual-Mode Approach for NoC Designs 669
Feasibility study and porting of the damped least square algorithm on FPGA 661
null 660
sysCgrid – SystemC grid simulation framework 616
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs 542
Coarse-Grained Reconfigurable Approach for Multi-Dataflow Systems 538
null 491
Reconfigurable Adaptive Multiple Transform Hardware Solutions for Versatile Video Coding 473
NeuPow: A CAD Methodology for High-level Power Estimation Based on Machine Learning 325
On-the-fly adaptivity for process networks over shared-memory platforms 301
The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design 272
Neu Pow: Artificial Neural Networks for Power and Behavioral Modeling of Arithmetic Components in 45nm ASICs Technology 271
Dataflow-functional high-level synthesis for coarse-grained reconfigurable accelerators 258
SS-design: Dataflow-based design of coarse-grained: Reconfigurable platforms reconfigurable platform composer tool project - Extended abstract 208
A coarse-grained reconfigurable wavelet denoiser exploiting the multi-dataflow composer tool 206
RVC: A multi-decoder CAL Composer tool 198
Hybrid switching techniques for heterogeneous traffic support in multi-processors system on chip and massively parallel processors 175
Profiling of Dataflow-Based Coarse-Grained Reconfigurable Platforms 173
null 153
A surface tension and coalescence model for dynamic distributed resources allocation in Massively Parallel Processors on-Chip 133
A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching 131
A Novel Non-Exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs 128
Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project 126
null 89
null 19
Totale 70.977
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Categoria #
all - tutte 83.928
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 83.928
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/2019520 0 0 0 0 0 0 0 0 0 0 271 249
2019/202014.981 649 419 87 350 4.850 3.722 2.068 436 562 700 443 695
2020/202121.645 1.034 748 1.077 6.347 4.205 1.955 1.821 1.164 587 931 1.157 619
2021/20225.174 590 489 243 304 411 501 192 145 402 627 716 554
2022/20236.806 371 678 539 625 609 826 438 642 472 516 683 407
2023/20246.492 398 302 300 405 651 1.371 845 613 349 609 649 0
Totale 70.977