UNICA IRIS Institutional Research Information System

PALUMBO, FRANCESCA
 Distribuzione geografica
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Continente #
EU - Europa 97.931
NA - Nord America 4.600
AS - Asia 1.570
SA - Sud America 226
AF - Africa 46
OC - Oceania 9
Continente sconosciuto - Info sul continente non disponibili 2
Totale 104.384
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Nazione #
IT - Italia 96.938
US - Stati Uniti d'America 4.540
CN - Cina 726
SG - Singapore 598
UA - Ucraina 270
SE - Svezia 228
BR - Brasile 191
DE - Germania 130
FI - Finlandia 91
VN - Vietnam 85
GB - Regno Unito 81
FR - Francia 47
CA - Canada 40
MA - Marocco 34
NL - Olanda 30
KR - Corea 25
IN - India 24
HK - Hong Kong 18
PL - Polonia 18
TR - Turchia 18
ES - Italia 17
MX - Messico 17
AT - Austria 16
IE - Irlanda 15
AR - Argentina 14
BE - Belgio 14
JP - Giappone 13
RU - Federazione Russa 12
BD - Bangladesh 9
CO - Colombia 7
IL - Israele 7
IR - Iran 6
SA - Arabia Saudita 6
AU - Australia 5
CZ - Repubblica Ceca 5
IQ - Iraq 5
LT - Lituania 5
ZA - Sudafrica 5
EC - Ecuador 4
BY - Bielorussia 3
CL - Cile 3
ID - Indonesia 3
JO - Giordania 3
NZ - Nuova Zelanda 3
PH - Filippine 3
PK - Pakistan 3
AZ - Azerbaigian 2
BO - Bolivia 2
DK - Danimarca 2
EU - Europa 2
HR - Croazia 2
KE - Kenya 2
KG - Kirghizistan 2
LV - Lettonia 2
PE - Perù 2
TW - Taiwan 2
UY - Uruguay 2
UZ - Uzbekistan 2
AE - Emirati Arabi Uniti 1
AL - Albania 1
AM - Armenia 1
BG - Bulgaria 1
CG - Congo 1
CI - Costa d'Avorio 1
CY - Cipro 1
DO - Repubblica Dominicana 1
EG - Egitto 1
GE - Georgia 1
GR - Grecia 1
IM - Isola di Man 1
JM - Giamaica 1
KZ - Kazakistan 1
LA - Repubblica Popolare Democratica del Laos 1
LK - Sri Lanka 1
MG - Madagascar 1
MY - Malesia 1
NO - Norvegia 1
OM - Oman 1
PR - Porto Rico 1
PS - Palestinian Territory 1
TV - Tuvalu 1
VE - Venezuela 1
ZW - Zimbabwe 1
Totale 104.384
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Città #
Cagliari 94.089
Uta 2.562
Fairfield 472
Ashburn 446
Woodbridge 385
Chandler 296
Dallas 280
Singapore 274
Houston 270
Boardman 215
Wilmington 205
Seattle 197
Ann Arbor 196
Cambridge 187
Beijing 162
Nyköping 157
Jacksonville 136
Dearborn 119
Los Angeles 103
Santa Clara 86
Shanghai 83
Nanjing 69
Helsinki 47
Hefei 45
Buffalo 43
Boston 41
Rome 34
Dong Ket 32
Casablanca 29
San Diego 29
Redwood City 27
Ho Chi Minh City 25
Atlanta 22
Seoul 22
New York 21
Amsterdam 20
Guangzhou 20
Nanchang 18
Chicago 17
Sassari 17
Tianjin 17
Brooklyn 16
Hong Kong 16
Nuremberg 16
São Paulo 16
Changsha 15
Dublin 15
Jiaxing 15
Milan 15
Mountain View 15
Brussels 14
Council Bluffs 14
Munich 14
Warsaw 14
Kunming 13
Denver 12
Hangzhou 12
La Maddalena 12
The Dalles 12
Tokyo 12
Turin 12
Jinan 11
Ottawa 11
Redondo Beach 11
Shenyang 11
Toronto 11
Washington 11
Düsseldorf 10
London 10
Montreal 10
Frankfurt am Main 9
Hebei 9
Orange 9
Phoenix 9
Vienna 9
Hanoi 8
Norwalk 8
Elk Grove Village 7
Alghero 6
Auburn Hills 6
Decimomannu 6
Lauterbourg 6
Madrid 6
Mexico City 6
Poplar 6
Quartu Sant'Elena 6
Salt Lake City 6
Xi'an 6
Azor 5
Columbus 5
Fuzhou 5
Rio de Janeiro 5
San Francisco 5
Stockholm 5
Ankara 4
Fortaleza 4
Gonnosfanàdiga 4
Irvine 4
Jinhua 4
Lappeenranta 4
Totale 102.073
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Nome #
MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation 3.366
Automated Design Flow for Multi-Functional Dataflow-Based Platforms 3.131
An FPGA platform for real-time simulation of spiking neuronal networks 3.027
Adaptable AES implementation with power-gating support 2.911
Neu Pow: Artificial Neural Networks for Power and Behavioral Modeling of Arithmetic Components in 45nm ASICs Technology 2.643
Optimization and deployment of CNNs at the Edge: The ALOHA experience 2.607
null 2.541
Modelling and automated implementation of optimal power saving strategies in coarse-grained reconfigurable architectures 2.536
Power modelling for saving strategies in coarse grained reconfigurable systems 2.522
Power and clock gating modelling in coarse grained reconfigurable systems 2.483
Exploring custom heterogeneous MPSoCs for real-time neural signal decoding 2.471
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing 2.387
Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy 2.376
An integrated hardware/software design methodology for signal processing systems 2.293
ALOHA: An architectural-aware framework for deep learning at the edge 2.262
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms 2.258
Reconfigurable Coprocessors Synthesis in the MPEG-RVC Domain 2.245
Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy 2.213
Profiling of Dataflow-Based Coarse-Grained Reconfigurable Platforms 2.047
Automated power gating methodology for dataflow-based reconfigurable systems 2.028
Computing swarms for self-adaptiveness and self-organizationin floating-point array processing 1.984
Runtime Energy versus Quality Tuning in Motion Compensation Filters for HEVC 1.885
Coarse-grained reconfiguration: dataflow-based power management 1.859
Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems 1.840
Hardware design methodology using lightweight dataflow and its integration with low power techniques 1.802
SS-design: Dataflow-based design of coarse-grained: Reconfigurable platforms reconfigurable platform composer tool project - Extended abstract 1.768
A nature-inspired adaptive floating-point coprocessing system 1.722
Dataflow-functional high-level synthesis for coarse-grained reconfigurable accelerators 1.718
null 1.697
Architecture-aware design and implementation of CNN algorithms for embedded inference: The ALOHA project 1.672
A coarse-grained reconfigurable approach for low-power spike sorting architectures 1.661
On-the-fly adaptivity for process networks over shared-memory platforms 1.638
Feasibility study of real-time spiking neural network simulations on a swarm intelligence based digital architecture 1.571
Automatic Generation of Dataflow-Based Reconfigurable Co-processing Units 1.545
Concurrent hybrid switching for massively parallel systems-on-chip: The CYBER architecture 1.434
null 1.423
Challenging CPS trade-off adaptivity with coarse-grained reconfiguration 1.266
CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of Reconfigurable systems in unceRtain hybRid envirOnments 1.221
A fast MPI-based parallel framework for cycle-accurate HDL multi-parametric simulations 1.141
Low power design methodology for signal processing systems using lightweight dataflow techniques 1.138
NeuPow: A CAD Methodology for High-level Power Estimation Based on Machine Learning 1.079
Feasibility study and porting of the damped least square algorithm on FPGA 1.027
Impact of half-duplex and full-duplex DMA Implementations on NoC performance 1.018
Design IP Faster: Introducing the C~ High-Level Language 930
Towards self-adaptive networks on chip for massively parallel processors: Multilevel quality of service programmability 925
The multi-dataflow composer tool: A runtime reconfigurable HDL platform composer 908
null 876
A coarse-grained reconfigurable wavelet denoiser exploiting the multi-dataflow composer tool 852
null 831
null 822
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs 808
Reconfigurable Adaptive Multiple Transform Hardware Solutions for Versatile Video Coding 785
RVC: A multi-decoder CAL Composer tool 768
Non-Exclusive Dual-Mode Approach for NoC Designs 763
sysCgrid – SystemC grid simulation framework 759
Coarse-Grained Reconfigurable Approach for Multi-Dataflow Systems 685
Demo: Reconfigurable Platform Composer Tool 676
The FitOptiVis ECSEL Project: Highly Efficient Distributed Embedded Image/Video Processing in Cyber-Physical Systems Invited Paper 661
A multithread AES accelerator for Cyber-Physical Systems 632
An Automated Design Flow for Adaptive Neural Network Hardware Accelerators 606
The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design 594
Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project 553
Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAPI 534
Multithread Accelerators on FPGAs: A Dataflow-Based Approach 469
A surface tension and coalescence model for dynamic distributed resources allocation in Massively Parallel Processors on-Chip 346
A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching 331
Hybrid switching techniques for heterogeneous traffic support in multi-processors system on chip and massively parallel processors 323
A Novel Non-Exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs 323
A Composable Monitoring System for Heterogeneous Embedded Platforms 304
Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project 209
PathTracer: Understanding Response Time of Signal Processing Applications on Heterogeneous MPSoCs 175
In-field automatic detection of grape bunches under a totally uncontrolled environment 170
A Dataflow Implementation of Inverse Kinematics on Reconfigurable Heterogeneous MPSoC 167
Unmanned vehicles in smart farming: A survey and a glance at future horizons 167
PathTracing: Raising the level of understanding of processing latency in heterogeneous MPSoCs 166
Elicitation of technical requirements in large research projects: The CERBERO approach 152
Reconfigurable and approximate computing for video coding 144
Adaptive software-augmented hardware reconfiguration with dataflow design automation 135
Message from the Program Chairs 131
MYRTUS: Multi-layer 360° dYnamic orchestration and interopeRable design environmenT for compute-continUum Systems 121
Dataflow modeling for reconfigurable signal processing systems 120
Exploring the performance of partially reconfigurable point-to-point interconnects 112
Cross-layer design of reconfigurable cyber-physical systems 105
Multi-Partner Project: Key Enabling Technologies for Cognitive Computing Continuum - MYRTUS Project Perspective 43
FPGA-based Implementation for Industrial Motion Control System 31
SECURED for health: Scaling up privacy to enable the integration of the european health data space 27
Integrating FPGA-Based Acceleration in Industrial Motion Control System 17
ONNX-To-Hardware Design Flow for Adaptive Neural-Network Inference on FPGAs 14
Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design 11
Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach 11
An FPGA-based accelerator design methodology for smart UAVs in precision agriculture: A case study 11
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs 10
Multi-purpose systems: A novel dataflow-based generation and mapping strategy 6
DSE and profiling of multi-context coarse-grained reconfigurable systems 5
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case 3
Totale 104.783
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Categoria #
all - tutte 128.458
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 128.458
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/20218.916 0 0 0 0 0 2.180 2.017 1.253 617 975 1.198 676
2021/20225.457 627 496 257 323 429 522 194 151 439 671 755 593
2022/20236.458 399 719 565 619 522 720 394 577 440 462 644 397
2023/20248.159 481 285 334 393 680 1.350 843 616 322 579 1.179 1.097
2024/202523.529 4.093 7.993 2.449 2.457 2.557 1.831 1.492 69 133 122 139 194
2025/20262.313 354 204 540 509 625 81 0 0 0 0 0 0
Totale 104.783