UNICA IRIS Institutional Research Information System

PALUMBO, FRANCESCA
 Distribuzione geografica
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Continente #
EU - Europa 100.086
NA - Nord America 5.472
AS - Asia 2.512
SA - Sud America 311
AF - Africa 71
OC - Oceania 9
Continente sconosciuto - Info sul continente non disponibili 2
Totale 108.463
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Nazione #
IT - Italia 98.894
US - Stati Uniti d'America 5.383
SG - Singapore 993
CN - Cina 927
UA - Ucraina 272
SE - Svezia 265
BR - Brasile 234
VN - Vietnam 209
DE - Germania 141
FI - Finlandia 138
FR - Francia 114
GB - Regno Unito 94
HK - Hong Kong 70
IN - India 67
BD - Bangladesh 57
CA - Canada 49
MA - Marocco 38
NL - Olanda 36
AR - Argentina 28
KR - Corea 25
MX - Messico 23
TR - Turchia 23
ES - Italia 20
PL - Polonia 20
IE - Irlanda 17
IQ - Iraq 17
JP - Giappone 17
AT - Austria 16
BE - Belgio 15
RU - Federazione Russa 14
CO - Colombia 12
PH - Filippine 12
PK - Pakistan 12
EC - Ecuador 11
IL - Israele 8
SA - Arabia Saudita 8
JM - Giamaica 7
LT - Lituania 7
UZ - Uzbekistan 7
ZA - Sudafrica 7
CL - Cile 6
ID - Indonesia 6
IR - Iran 6
JO - Giordania 6
MY - Malesia 6
VE - Venezuela 6
AU - Australia 5
AZ - Azerbaigian 5
CZ - Repubblica Ceca 5
KE - Kenya 5
PE - Perù 5
TN - Tunisia 5
BO - Bolivia 4
EG - Egitto 4
AE - Emirati Arabi Uniti 3
BY - Bielorussia 3
CR - Costa Rica 3
NP - Nepal 3
NZ - Nuova Zelanda 3
PS - Palestinian Territory 3
TW - Taiwan 3
AL - Albania 2
BG - Bulgaria 2
DK - Danimarca 2
DZ - Algeria 2
ET - Etiopia 2
EU - Europa 2
HR - Croazia 2
KG - Kirghizistan 2
KZ - Kazakistan 2
LV - Lettonia 2
PR - Porto Rico 2
PY - Paraguay 2
QA - Qatar 2
TH - Thailandia 2
UY - Uruguay 2
AM - Armenia 1
BF - Burkina Faso 1
BH - Bahrain 1
CG - Congo 1
CH - Svizzera 1
CI - Costa d'Avorio 1
CY - Cipro 1
DO - Repubblica Dominicana 1
GE - Georgia 1
GR - Grecia 1
HN - Honduras 1
IM - Isola di Man 1
KW - Kuwait 1
LA - Repubblica Popolare Democratica del Laos 1
LB - Libano 1
LK - Sri Lanka 1
LY - Libia 1
MG - Madagascar 1
MN - Mongolia 1
MU - Mauritius 1
NI - Nicaragua 1
NO - Norvegia 1
OM - Oman 1
PA - Panama 1
Totale 108.456
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Città #
Cagliari 96.001
Uta 2.562
Ashburn 538
Singapore 527
Fairfield 472
Woodbridge 385
San Jose 359
Chandler 296
Dallas 289
Houston 275
Boardman 236
Wilmington 206
Seattle 197
Ann Arbor 196
Cambridge 187
Beijing 174
Nyköping 157
Jacksonville 137
Los Angeles 134
Dearborn 119
Santa Clara 100
Helsinki 87
Shanghai 87
Nanjing 69
Hong Kong 66
Lauterbourg 66
Ho Chi Minh City 65
Council Bluffs 57
New York 48
Buffalo 46
Hefei 45
Boston 42
Rome 42
Dong Ket 32
Hanoi 32
San Diego 31
Casablanca 30
Atlanta 29
The Dalles 29
Redwood City 28
Guangzhou 26
Amsterdam 24
Seoul 22
Chicago 21
São Paulo 20
Orem 19
Tianjin 19
Brooklyn 18
Nanchang 18
Nuremberg 18
Changsha 17
Dublin 17
Milan 17
Sassari 17
Warsaw 16
Brussels 15
Frankfurt am Main 15
Jiaxing 15
Montreal 15
Mountain View 15
Munich 15
Chennai 14
Denver 13
Hangzhou 13
Kunming 13
Tokyo 13
Toronto 13
Turin 13
La Maddalena 12
London 12
Shenyang 12
Washington 12
Jinan 11
Lappeenranta 11
Ottawa 11
Phoenix 11
Redondo Beach 11
Düsseldorf 10
Mumbai 10
Hebei 9
Orange 9
Vienna 9
Haiphong 8
Mexico City 8
Norwalk 8
Shenzhen 8
Elk Grove Village 7
Madrid 7
Philadelphia 7
Tashkent 7
Xi'an 7
Alghero 6
Amman 6
Auburn Hills 6
Brasília 6
Columbus 6
Da Nang 6
Decimomannu 6
Lahore 6
Manchester 6
Totale 105.220
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Nome #
MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation 3.408
Automated Design Flow for Multi-Functional Dataflow-Based Platforms 3.174
An FPGA platform for real-time simulation of spiking neuronal networks 3.070
Adaptable AES implementation with power-gating support 2.957
Neu Pow: Artificial Neural Networks for Power and Behavioral Modeling of Arithmetic Components in 45nm ASICs Technology 2.693
Optimization and deployment of CNNs at the Edge: The ALOHA experience 2.662
Modelling and automated implementation of optimal power saving strategies in coarse-grained reconfigurable architectures 2.610
Power modelling for saving strategies in coarse grained reconfigurable systems 2.583
null 2.541
Power and clock gating modelling in coarse grained reconfigurable systems 2.537
Exploring custom heterogeneous MPSoCs for real-time neural signal decoding 2.526
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing 2.467
Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy 2.403
An integrated hardware/software design methodology for signal processing systems 2.335
ALOHA: An architectural-aware framework for deep learning at the edge 2.315
Reconfigurable Coprocessors Synthesis in the MPEG-RVC Domain 2.306
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms 2.294
Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy 2.262
Profiling of Dataflow-Based Coarse-Grained Reconfigurable Platforms 2.086
Automated power gating methodology for dataflow-based reconfigurable systems 2.080
Computing swarms for self-adaptiveness and self-organizationin floating-point array processing 2.033
Runtime Energy versus Quality Tuning in Motion Compensation Filters for HEVC 1.935
Coarse-grained reconfiguration: dataflow-based power management 1.918
Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems 1.877
Hardware design methodology using lightweight dataflow and its integration with low power techniques 1.850
SS-design: Dataflow-based design of coarse-grained: Reconfigurable platforms reconfigurable platform composer tool project - Extended abstract 1.823
A nature-inspired adaptive floating-point coprocessing system 1.763
Dataflow-functional high-level synthesis for coarse-grained reconfigurable accelerators 1.761
Architecture-aware design and implementation of CNN algorithms for embedded inference: The ALOHA project 1.728
On-the-fly adaptivity for process networks over shared-memory platforms 1.703
null 1.697
A coarse-grained reconfigurable approach for low-power spike sorting architectures 1.693
Automatic Generation of Dataflow-Based Reconfigurable Co-processing Units 1.595
Feasibility study of real-time spiking neural network simulations on a swarm intelligence based digital architecture 1.571
Concurrent hybrid switching for massively parallel systems-on-chip: The CYBER architecture 1.463
null 1.423
Challenging CPS trade-off adaptivity with coarse-grained reconfiguration 1.266
CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of Reconfigurable systems in unceRtain hybRid envirOnments 1.221
A fast MPI-based parallel framework for cycle-accurate HDL multi-parametric simulations 1.168
Low power design methodology for signal processing systems using lightweight dataflow techniques 1.138
NeuPow: A CAD Methodology for High-level Power Estimation Based on Machine Learning 1.131
Feasibility study and porting of the damped least square algorithm on FPGA 1.078
Impact of half-duplex and full-duplex DMA Implementations on NoC performance 1.049
Design IP Faster: Introducing the C~ High-Level Language 970
Towards self-adaptive networks on chip for massively parallel processors: Multilevel quality of service programmability 961
The multi-dataflow composer tool: A runtime reconfigurable HDL platform composer 942
A coarse-grained reconfigurable wavelet denoiser exploiting the multi-dataflow composer tool 900
null 876
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs 861
null 831
null 822
Reconfigurable Adaptive Multiple Transform Hardware Solutions for Versatile Video Coding 822
RVC: A multi-decoder CAL Composer tool 800
sysCgrid – SystemC grid simulation framework 785
Non-Exclusive Dual-Mode Approach for NoC Designs 779
Coarse-Grained Reconfigurable Approach for Multi-Dataflow Systems 730
Demo: Reconfigurable Platform Composer Tool 725
A multithread AES accelerator for Cyber-Physical Systems 694
An Automated Design Flow for Adaptive Neural Network Hardware Accelerators 676
The FitOptiVis ECSEL Project: Highly Efficient Distributed Embedded Image/Video Processing in Cyber-Physical Systems Invited Paper 661
The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design 642
Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project 596
Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAPI 583
Multithread Accelerators on FPGAs: A Dataflow-Based Approach 524
A surface tension and coalescence model for dynamic distributed resources allocation in Massively Parallel Processors on-Chip 382
A Composable Monitoring System for Heterogeneous Embedded Platforms 370
Hybrid switching techniques for heterogeneous traffic support in multi-processors system on chip and massively parallel processors 359
A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching 357
A Novel Non-Exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs 352
Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project 272
PathTracer: Understanding Response Time of Signal Processing Applications on Heterogeneous MPSoCs 244
In-field automatic detection of grape bunches under a totally uncontrolled environment 232
MYRTUS: Multi-layer 360° dYnamic orchestration and interopeRable design environmenT for compute-continUum Systems 231
A Dataflow Implementation of Inverse Kinematics on Reconfigurable Heterogeneous MPSoC 226
PathTracing: Raising the level of understanding of processing latency in heterogeneous MPSoCs 220
Unmanned vehicles in smart farming: A survey and a glance at future horizons 218
Elicitation of technical requirements in large research projects: The CERBERO approach 186
Reconfigurable and approximate computing for video coding 174
Adaptive software-augmented hardware reconfiguration with dataflow design automation 173
Message from the Program Chairs 161
Dataflow modeling for reconfigurable signal processing systems 138
Cross-layer design of reconfigurable cyber-physical systems 137
Exploring the performance of partially reconfigurable point-to-point interconnects 129
Runtime reconfigurable FPGA accelerator for tactile texture classification based shallow CNN 99
Multi-Partner Project: Key Enabling Technologies for Cognitive Computing Continuum - MYRTUS Project Perspective 92
An FPGA-based accelerator design methodology for smart UAVs in precision agriculture: A case study 86
FPGA-based Implementation for Industrial Motion Control System 81
Adaptive CNN acceleration on FPGAs: closing the gap with state-of-the-art solutions 80
ONNX-To-Hardware Design Flow for Adaptive Neural-Network Inference on FPGAs 78
Integrating FPGA-Based Acceleration in Industrial Motion Control System 76
SECURED for health: Scaling up privacy to enable the integration of the european health data space 72
Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach 60
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs 54
Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design 52
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case 43
DSE and profiling of multi-context coarse-grained reconfigurable systems 33
Multi-purpose systems: A novel dataflow-based generation and mapping strategy 32
Totale 108.872
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Categoria #
all - tutte 135.675
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 135.675
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021676 0 0 0 0 0 0 0 0 0 0 0 676
2021/20225.457 627 496 257 323 429 522 194 151 439 671 755 593
2022/20236.458 399 719 565 619 522 720 394 577 440 462 644 397
2023/20248.159 481 285 334 393 680 1.350 843 616 322 579 1.179 1.097
2024/202523.529 4.093 7.993 2.449 2.457 2.557 1.831 1.492 69 133 122 139 194
2025/20266.402 354 204 540 509 625 425 1.142 641 415 933 440 174
Totale 108.872